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Today, let’s talk about the RS-485 bus. RS-485 is also a very widely used communication interface. This article will discuss the key points, and it is a bit long, about 5000 words.

The Past and Present

RS-485, what does RS mean? It stands for Recommended Standard, which means a recommended standard. 485 is the standard identification number, and there is no need to delve into why this identification number was set. RS-485 is also known as ANSI/TIA/EIA-485, where these prefixes are abbreviations of standard associations. For example, EIA is the abbreviation for the Electronics Industries Association. In 1983, the RS-485 communication interface was approved by the Electronics Industries Association as a communication interface standard.

Even today, in the era of booming IoT, RS-485 still has a large number of applications. Many protocols use RS-485 as the physical layer. What are some commonly used standard protocols that utilize RS-485 as the physical layer? For example:

• Industrial HART Bus
• Modbus Protocol
• Profibus DP
• …….

Electrical Characteristics

Signal sampling is done through differential mode transmission, which is relative to common mode. Differential mode is also known as differential transmission. So what kind of transmission is differential mode? A picture is worth a thousand words; just look at the two diagrams below:

Common Mode Transmission

When using common mode transmission, common mode noise will superimpose on the final output signal, polluting the original signal.

Differential Mode Transmission

In differential mode transmission, the signals emitted from the source have opposite phases for signal + and signal -. For common mode noise, it exists on both +/- lines. Ideally, they are equal in amplitude and in phase, while the receiving end acts like a subtractor; useful signals are retained due to the opposite phase, while noise is canceled. In practical circuits, this will significantly weaken.

Thus, it can be seen that differential mode transmission has an advantage over common mode transmission because it can effectively cancel common mode interference.

Differential mode is also referred to as balanced mode in some places, while common mode is referred to as unbalanced mode.

Regarding this interference, let’s take a look at a waveform:

At the edges of the A/B signals, the waveforms are slightly distorted, but when you look at A-B (the red line is the oscilloscope’s MATH subtraction function for A-B), the edge becomes very clean! This example illustrates how differential mode transmission can effectively resist common mode interference.

Electrical Parameters

The electrical parameters of RS-485 are:

• Common mode voltage range is -7 to +12V
• Supports up to 32 multipoint topology connections, see the network topology diagram below
• Using a 40-foot cable, the transmission rate can reach 10Mbps; 1 foot is equivalent to 30.48cm, and Mbps means megabits per second
• Using a 4000-foot cable, the transmission rate can reach 100kbps
• Half-duplex communication
• Minimum differential voltage tolerance: 200mV, meaning that if the differential voltage is below 200mV at the receiving end, it cannot correctly identify 0/1. How should this be understood?

How should the above diagram be understood? The RS-485 transceiver’s sending circuit must provide at least 1.5V differential voltage output capability. Due to line impedance attenuation, 32 receiving circuit input impedances, and 120Ω termination resistors, the amplitude of the differential signal will gradually attenuate. Therefore, at the very end, at least 200mV of differential voltage must be provided to the terminal receiving circuit.

: For the receiving circuit, it determines the difference between the common mode voltage of line A and line B:

• If , then the receiving circuit R recognizes it as logic 1
• If , then the receiving circuit R recognizes it as logic 0

Simply put, if the absolute voltage of line A is at least 200mV greater than that of line B, it is recognized as logic 1; or if the absolute voltage of line A is at least 200mV lower than that of line B, it is recognized as logic 0.

The parameters here should be theoretical values under certain characteristic impedance cables, and adjustments and on-site testing are required during actual engineering use. It is generally advisable not to exceed these theoretical limits.

Speaking of electrical characteristic parameters, let’s first look at a general interface circuit:

From this interface circuit, there are several key points:

• RS-485 communication from the microcontroller/DSP/processor interface uses the UART interface with the RS-485 transceiver interface. Of course, you might ask if I can use an FPGA? Certainly, you can implement a serial transceiver IP module with an FPGA. You might even say that I can simulate UART with GPIO; this can also be done, but it is not very meaningful as it would occupy CPU resources to implement the lower-level BIT transmission.
• As mentioned earlier, half-duplex implies that there is full-duplex. What is half-duplex? First, half-duplex and full-duplex are defined in a point-to-point context. Here, point-to-point means at the same time, where half-duplex means that the device is either receiving data or sending data at the same time, not allowing simultaneous transmission and reception.
  Full-duplex, on the other hand, allows for simultaneous transmission and reception. For example, the I2C bus is a half-duplex bus, while a 4-wire SPI is full-duplex, and a 3-wire SPI is a half-duplex bus; RS-422 and RS-232 are full-duplex interfaces; whereas the CAN bus is a half-duplex bus. RS-485 is a half-duplex bus:

• When the Host sends data, the data travels along the red line through the twisted pair to the differential receiving circuit of the Slave. When the slave responds, the data travels along the blue direction to the Host’s receiving circuit. However, since the transmission medium is a pair of twisted wires, one side cannot transmit signals while the other side is sending data. From the transceiver’s control perspective:

  A GPIO pin is used to control the receive/transmit enable. A block diagram of the chip’s internal principle makes it easy to understand:

• When DIR=0, the receiving circuit is enabled, and the sending circuit is disabled (DE=0), which is equivalent to high impedance for the bus; when DIR=1, the receiving circuit is enabled, and the sending circuit is disabled (DE=1), the A/B signal on the bus depends on the DI signal. There are two questions here:

  1. Why does the chip design to be opposite effective logic? This is also to facilitate the control of the receive/transmit circuit with a single GPIO.

  2. Why doesn’t the transceiver chip use a single pin for receive/transmit enable? For example, why not just call it DIR? It could also be done with two pins for separate control for receiving/sending:
  
• It is even possible to set DE=1 to 0 when DE=1, which would allow for self-looping. This design can be implemented in products to allow for self-diagnosis of the transceiver and wiring by comparing the received messages with the sent messages. This can diagnose issues like chip soldering, transceiver damage, or short circuits in the wiring.

  However, you might say, this is nonsense! You just said that RS-485 cannot transmit and receive at the same time, and now you’re saying it can; isn’t that contradictory? It is not contradictory; the inability to transmit and receive simultaneously refers to not being able to receive transmission messages from other devices while sending, while the receiving here is the message sent by itself.

  Therefore, the essence of half-duplex is that the communication medium does not have a bidirectional channel. When sending data to the bus, the medium is occupied, and even if one wants to send, it cannot correctly send the signal to the medium. If forced to send, the data will be disordered, and the transceiver chip may even be damaged.

• : Receiver Output Enable, receiver enable,
• DE: Driver Output Enable, driver output enable
• The DIR pin in the diagram controls whether the current RS-485 is in “receive” or “send” mode.

Earlier, we mentioned the common mode voltage indicators and differential mode transmission; let’s take a look at the waveform:

Channel CH2 connects to the 485 output A, and CH3 connects to the 485 output A. The red line shows the oscilloscope’s MATH function: CH2-CH3. Most oscilloscopes have mathematical operation functions.

If you want to see the differential signal, you can use a dual-channel oscilloscope with the MATH subtraction function. If some oscilloscopes do not have the MATH function, there is another trick:

Invert the negative terminal of channel B, or the differential signal, and move channel B up to coincide with the idle level; this will make it more intuitive to see A-B, right?

Through this diagram, what valuable signal characteristics can be discovered?

• Signal A is high when idle; signal B is low when idle. Therefore, you will see devices labeled 485_A+ and 485_B-.
• Each channel’s common mode voltage value is within the standard requirement of -7 to 12V, with signal A at 4V and signal B at 5V:

How should the data be interpreted?

The captured data is a MODBUS-RTU master sending to a slave device. The first two bytes are 0x01 0x03, with the UART mode having 1 start bit, 8 data bits, 1 stop bit, no parity, and low bit first. In this example, the UART communication format is

First, based on the UART communication mode, we calculate several parameters, including the bit time and byte time:

This diagram shows that the width of the start bit is exactly 104us.

For parsing such asynchronous serial timing waveforms, the most important thing is to calculate the bit time and byte time according to the communication format, which allows for direct waveform data parsing. Thinking from this perspective, if you want to use an FPGA to implement a UART protocol logic analyzer, this is the core indicator. Let me act as a visual UART logic analyzer:

The time width of the 8-bit data is exactly 832us, and since the format is low bit first, it must be viewed in reverse, which matches the actual sent data 0x01 0x03.

When debugging at the lower level, if issues arise, this method can be used to check whether the software correctly drives the hardware. For example, similar methods can be used to inspect hardware waveforms when debugging I2C/SPI and other lower-level interfaces; the only difference is that I2C/SPI belongs to synchronous communication, which means that its communication base has a synchronous clock signal, with I2C’s SCL and SPI’s SCK being synchronous clock signals.

Driving Capability

The maximum electrical driving capability of RS-485 is summarized in the electrical parameters. Under the multipoint network topology, it can drive up to 32 stations. How should this indicator be interpreted?

First, let’s examine the characteristics of a station’s receiving and sending circuit. The standard equivalent input impedance of the receiver circuit of the transceiver is 12kΩ. For example, looking at the MAX 485 datasheet:

Why is it 32? This is mainly due to the previously mentioned 200mV minimum driving capability requirement.

It can also be understood this way: each receiving circuit’s input impedance is not ideally high, but is 12kΩ. For instance, if one station sends, it is equivalent to having 32 stations’ input impedances in parallel. Why 32? Don’t forget that the sending station itself also has a receiving circuit, so without considering termination resistors and line impedances, the sending circuit sees an equivalent load:

Thus, the sending circuit’s driving capability is limited, which makes it easier to understand.

The diagram below illustrates the so-called multipoint network topology, where all stations are connected along the twisted pair on the bus.

Therefore, you might see the term “one unit RS-485 load” in some places. The so-called unit load refers to the 12kΩ standard input impedance, which is defined by the EIA-485 standard. Thus, terms like unit load originate from this.

Data Monitoring

For example, in a Modbus-RTU multipoint network based on RS-485, when programming protocols or debugging actual multi-station buses, it may be necessary to monitor all messages on the bus. It is even possible to implement a bus message recorder that records all messages on the bus. How should this be implemented?

Buy a USB to RS-485 converter or make one yourself. Connect the A/B lines to the bus and plug the USB into a computer. Using a serial monitoring terminal or writing a small serial receiving software, you can monitor all messages on the bus.

For instance, the AccessPort serial tool is quite useful:

Application Design

In application design, these dimensions need to be considered:

• Termination Design
• Interface Chip
• Isolation Design

Termination Design

First, why is termination necessary? This is because RS-485 uses twisted pair transmission, and the standard specifies that the differential characteristic impedance of twisted pairs is between 100Ω and 150Ω. The RS-485 standard setters chose 120Ω as the nominal characteristic impedance.

Assuming a signal is sent from the left station, if there is no termination, the signal’s impedance is continuous during transmission, but when it reaches the right side, the equivalent impedance becomes the input impedance of the receiving circuit, which might be 12kΩ, leading to a discontinuity in impedance, causing an impedance jump! A portion of the signal’s energy will return along the original path, and due to capacitance and inductance, a phase difference will occur. The reflected signal will superimpose on the original signal, which can cause communication errors. In severe cases, communication may fail altogether.

To gain a deeper understanding of the underlying principles, one can study transmission line theory.

Perhaps friends who have worked with Profibus DP (which also uses RS-485 at the physical layer) might say, why does Profibus DP recommend the termination matching circuit shown below?

Actually, it is because the communication medium used by Profibus DP has a different nominal characteristic impedance. Therefore, there will be slight differences in practical engineering applications.

I saw this termination method in TI’s materials:

In environments with significant noise, it is recommended to use the right termination scheme, utilizing two 60Ω resistors and a 220pF capacitor to form a low-pass filter, which will enhance the line’s noise resistance.

When wiring in actual engineering, if encountering significant noise, one can use an oscilloscope to check the bus signal quality and make small adjustments to the termination method.

Interface Design

Many chip manufacturers, such as TI and Microchip, provide RS-485 transceiver chips. When selecting an interface chip, it is important to consider whether the chip’s power supply voltage input logic is compatible with the levels of the microcontroller/DSP being used. Additionally, it is essential to ensure that the receiving circuit’s impedance complies with the standard RS-485 input impedance. If not, adjustments may be required regarding the number of loads that can be carried during network deployment. Also, note that some newly designed RS-485 transceivers come with fail-safe features.

Moreover, as previously mentioned, standard transceivers can drive 32 standard load devices, which corresponds to the (12kΩ) standard unit input impedance.

When designing specific interface circuits, EMC requirements must also be considered. In some field devices, strong interference may occur, such as large inductive devices running on the power grid. Additionally, there may be spatial radiation interference, in which case one might consider using shielded twisted pairs with the shield connected to ground. My understanding of interference resistance is not very deep, but I will summarize it here. I saw a lightning protection interface circuit design scheme, which can be referenced:

https://www.programmersought.com/article/95833359295/

Previously, it was mentioned that the standard RS-485 can accommodate 32 standard receiving impedance devices. What if you want to connect more than 32 station devices in an actual system? You can design a relay device to connect two network segments using a relay to solve the problem of insufficient driving capability. Of course, there are also ready-made products available.

Isolation Design

Why is isolation necessary? It is to reduce ground noise. In many field environments, there may be large current switching devices, inductive devices, etc., and noise can easily couple into the device through the communication ground. Especially in industrial devices, interfaces are generally designed to be isolated. To design an isolated interface, one can consider using chips with isolation functions, such as ADI’s iCoupler technology products ADM2481 and ADM2485. Alternatively, one can use optocouplers with standard RS-485 transceivers. The only thing to note is that an isolated power supply must be designed to power the circuits on both sides of the isolation.

The diagram above is from TI’s “The RS-485 Design Guide,” which is a very good document, and many parts of this article are also organized based on this document. If you are interested in this document, you can reply with 485 to automatically receive it.

In Summary

RS-485 may seem simple, but there are many aspects that need to be understood and noted during application design. Often, what makes a robust product is not the overall direction but the small details that can easily lead to product instability.

References: TI: The RS-485 Design Guide

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