Japanese semiconductor giant Renesas Electronics has launched an MCU product for edge AI, enhancing AI performance by up to 30 times, and is manufactured by TSMC using a 22nm process. Renesas announced the availability of the edge AI MCU product RA8P1, which has entered mass production, achieving inference processing performance over 30 times that of … Read more
Overview 1.1 What is the SWD Protocol SWD (Serial Wire Debug) is a two-wire debugging interface protocol developed by ARM, specifically designed for debugging and programming Cortex-M series microcontrollers. As a replacement for the traditional JTAG interface, SWD significantly reduces the number of pins while maintaining powerful debugging capabilities, making it the mainstream choice for … Read more
Scan to FollowLearn Embedded Systems Together, learn and grow together Overview 1.1 What is the SWD Protocol SWD (Serial Wire Debug) is a two-wire debugging interface protocol developed by ARM, specifically designed for debugging and programming Cortex-M series microcontrollers. As a replacement for the traditional JTAG interface, SWD significantly reduces the number of pins while … Read more
Dear friends, today I would like to introduce you to Tock. You might find this name a bit unfamiliar, but once you learn about its powerful features, you will definitely fall in love with this operating system. Especially if you are involved in embedded system development, this article will be helpful for you! What is … Read more
Definition First, let’s look at the definitions of both in the authoritative guide for Cortex-M. 1 Exception Definition According to the authoritative guide for Cortex-M, an exception refers to an event that can alter the normal program flow. When an exception occurs, the processor pauses the currently executing task and executes a dedicated program to … Read more
The Cortex-M3 and Cortex-M4 processors utilize a 32-bit architecture, with internal registers in the register set, a 32-bit data path, and bus interfaces, employing Thumb-2 technology that supports both 16-bit and 32-bit instructions. They feature the following characteristics: Three-stage pipeline design Harvard bus architecture (I-BUS, D-BUS) 32-bit addressing AMBA bus interface NVIC interrupt controller, supporting … Read more
1. Introduction In embedded system development, the HardFault exception of Cortex-M microcontrollers is one of the most challenging issues. When the system encounters a severe error that cannot be handled, it triggers a HardFault interrupt, causing the program to stop running. This exception is often caused by memory access errors, stack overflows, illegal instruction executions, … Read more
In embedded development, handling asynchronous events is an unavoidable challenge. For instance, reading sensor data from an accelerometer to calculate steps, or triggering RTOS context switches via timers, all rely on the support of exception handling mechanisms. Today, we will discuss the exception handling model of ARM Cortex-M. The Core of Exception Handling In the … Read more
Commonly used microcontrollers for industrial-grade equipment can be broadly divided into HC32L110C6PA-TSSOP20TR and HC32L136K8T6-LQFP64, both produced by Holtek. 1. HC32L110C6PA-TSSOP20TR Core Architecture: 32-bit ARM Cortex-M0+ core Maximum Clock Frequency: 48MHz Memory: Flash 64KB, SRAM 8KB Pin Count: 20 pins (TSSOP package) Operating Voltage: 2.4V ~ 3.6V Peripheral Interfaces: UART, SPI, I2C, ADC (12-bit resolution), Timer, … Read more
Source: https://blog.csdn.net/qq_34430371/article/details/125820927 Compiled by: Technology Makes Dreams Greater | Li Xiaoyao The author discusses the understanding and insights regarding ARM general purpose registers and status registers. ARM General Purpose Registers For processors, registers can serve as temporary storage for holding intermediate results, as input data for computations, or as an index for accessing memory, with … Read more