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Overview of ZYNQ
ZYNQ mainly consists of two parts:
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Processing System (PS): The upper left part of the above image is the PS part, which includes:
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Symmetric Multi-Processing (SMP) with dual-core ARM Cortex A9 -
Rich peripherals: 2×SPI, 2×I2C, 2×CAN, 2×UART, 2×SDIO, 2×USB, 2×GigE, GPIO -
Static Memory Controller: Quad-SPI, NAND, NOR -
Dynamic Memory Controller: DDR3, DDR2, LPDDR2 -
Programmable Logic (PL): Compatible with Xilinx 7 series FPGA
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Artix™ based chips: Z-7010 and Z-7020 -
Kintex™ based chips: Z-7030 and Z-7045
All peripherals of the ZYNQ processing system (PS) are connected to the AMBA (Advanced Microcontroller Bus Architecture) bus, and the IP designed based on FPGA can be mounted on the AMBA bus through the AXI interface, enabling interconnection among internal components. This involves two concepts:
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The AMBA bus, which friends familiar with ARM architecture should generally understand, is a registered trademark of ARM. It is an open standard on-chip interconnect specification for connecting and managing functional blocks in System-on-Chip (SoC) designs. It facilitates the development of multi-core processor designs with bus structures and multiple controllers or components. Since its inception, AMBA has been widely used, far exceeding the microcontroller device domain. Today, AMBA is widely used in various ASIC and SoC components, including application processors used in modern portable mobile devices. -
The Advanced eXtensible Interface (AXI): Part of ARM’s AMBA 3.0 and AMBA 4.0 specifications, it is a parallel high-performance, synchronous, high-frequency, multi-master, multi-slave communication interface primarily designed for on-chip communication. Why is AXI considered part of AMBA? The following two diagrams can help clarify.
High Flexibility of ZYNQ
Flexible PS Side I/O Multiplexing
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Multiplexed I/O (MIO): PS side peripheral I/O multiplexing, what is this concept? The previous introduction mentioned that ZYNQ is mainly divided into PS/PL two major modules, the peripherals on the PS side such as USB/CAN/GPIO/UART need pins to interact with the outside world. The so-called multiplexing here is similar to the pin multiplexing concept in common microcontrollers and processors. However (this is key), ZYNQ supports up to 54 PS pins for MIO, providing very high flexibility for configuration, greatly facilitating hardware design and PCB layout! The configuration of MIO can be flexibly achieved using Vivado software, as shown in the figure below.
Hardware engineers often find it challenging to layout and wire complex systems, often falling into EMC pitfalls due to unreasonable layouts. The high flexibility of ZYNQ’s I/O pins undoubtedly provides great convenience in circuit design, allowing for very flexible PCB layout and routing, thus significantly improving EMC performance.
Flexible PS-PL Interconnection Interfaces
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Extended Multiplexed I/O (EMIO): If you want to access PL through PS without wasting the AXI bus, you can use the EMIO interface to access PL. Among the 54 I/O pins, some can only be used for MIO, most can be used for either MIO or EMIO, and a few pins can only be accessed through EMIO.
As shown in the figure, for example, I2C0 can be mapped to the PL side pins output via EMIO, which undoubtedly increases flexibility!
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PS-PL Interface HP0-HP3: As shown in the architecture diagram, AXI high-performance slave ports (HP0-HP3) implement the PS-PL interface.
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Configurable 32-bit or 64-bit data width -
Can only access on-chip memory (OCM) and DDR -
AXI FIFO interface (AFI) uses 1KB FIFOs to buffer large data transfers -
PS-PL Interface GP0-GP1: As shown in the architecture diagram, AXI general-purpose ports.
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Two PS master interfaces connect to two PL slave devices -
32-bit data width -
A 64-bit accelerator coherent port (ACP) AXI slave interface connected to CPU memory, ACP is a 64-bit slave interface on the SCU (coherence control unit), providing an asynchronous cache coherence access point from PL to PS. ACP can be accessed by many PL masters to achieve the same way of accessing the memory subsystem as the APU processor. This improves overall performance, reduces power consumption, and simplifies software. The performance of the ACP interface is the same as that of the standard AXI slave interface, supporting most standard read and write operations without the need for additional coherence operations in the PL components.
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DMA, interrupts, event signals:
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Processor event bus signals events to the CPU -
PL peripheral IP interrupts to PS general interrupt controller (GIC) -
Four DMA channel RDY/ACK signals -
Extended Multiplexed I/O (EMIO) allows PS peripheral ports to access PL logic and device I/O pins.
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Clock and reset signals:
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Four PS clock enable control connected to PL -
Four PS reset signals connected to PL
Flexible Clock System
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PS clock sources: -
PS side has 4 external clock source pins -
PS side has 3 PLL clock modules -
PS side has 4 clock sources that can output to PL -
PL side has 7 clock sources -
PL side clock source domain is different from PS side -
PL side clock can flexibly come from external pins on the PL side due to the hard programmability of FPGA, allowing for complete flexible configuration -
Can also use the 4 clock sources from the PS side -
Note -
Clock synchronization between PL and PS is handled by the PS side -
PL cannot provide clocks for PS use
Rich IP Library
Zynq is a SoC with a large number of standard IPs that no longer need to be redesigned and can be used directly. This enhances the design abstraction level, and reusing pre-tested and verified components accelerates development while reducing costs. As the saying goes: “Why reinvent the wheel?”.
Vivado comes with a large number of IPs for use, such as mathematical computation IP, signal processing IP, image video processing IP, communication interconnect (Ethernet, DDS, modulation, software radio, error correction), processor IP (MicroBlaze, etc.), and even artificial intelligence algorithm IP.
For instance, signal processing IP, due to the use of FPGA hard logic for signal processing without CPU computation, has a significant advantage in implementing complex signal calculations (such as implementing a very high-order FIR filter, multi-point FFT calculation).
Dual ARM Hard Core Processors
As shown in the architecture diagram, ZYNQ has dual ARM Cortex-A9 hard cores built-in, providing significant flexibility in software design. Complex operating systems such as Linux and Android can run on this processor. Compared to conventional FPGA soft core IP approaches, it has stronger computational processing capabilities. You might say that its processing power compared to other current ARM chips is slightly insufficient, but it can basically meet the needs of conventional embedded system applications in medical, industrial fields, etc.
Organic Combination of PL/PS
From the previous brief analysis, it is not difficult to see that the combination of programmable hardware logic and processor units in PL is very well done.
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PL side: Can design a highly flexible peripheral system, while programmable hardware logic circuits can achieve true hard parallel processing and hard real-time systems. -
PS side: The organic combination of PL and PS allows for centralized software management of such high flexibility, hard parallel, and hard real-time processing systems.
Imagine if a system needs to achieve hard real-time, hard parallel, and complex peripheral interconnection systems:
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Perhaps a multi-microcontroller (such as a microcontroller) + processor scheme would be adopted, where the microprocessor meets real-time requirements, and the processor runs Linux to implement upper-level business logic. -
Or use FPGA + processor to achieve.
Both of these solutions have very high technical complexity, with complex hardware circuit PCB designs, and software development and maintenance will also increase complexity. ZYNQ can very well meet the design requirements of such systems, truly achieving system on chip, which is also a good reflection of SoC.
In Summary
The high flexibility of ZYNQ, rich peripherals, extensive IP library, and the powerful and easy-to-use development environment of Vivado bring many advantages to embedded system design using ZYNQ.
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