I have a black leather notebook that I’ve been using since 2001, with the National Semiconductor logo on its cover. It holds sentimental value for me. Firstly, it reminds me of the breakfast I had with attendees at a National Semiconductor executive event in Laguna Niguel, California, on September 11, 2001. That morning, we were … Read more
SiFive’s Best Processor Portfolio We are excited to announce that the SiFive 20G1 version has undergone a comprehensive update and upgrade to its RISC-V IP portfolio. The release of version 20G1 brings enhancements and new features to the SiFive Core IP, which is the most widely used RISC-V IP portfolio in the industry. This portfolio … Read more
Access, Inspect, and Control The term “debug” has a legendary history. According to various sources, the word debug was coined in 1945 by computer pioneer and U.S. Navy Rear Admiral Grace Hopper when she removed a moth from the Harvard Mark II computer. The use of the word bug can also be traced back to … Read more
★ Click the blue text above to follow us with one click ★ With the continuous improvement of embedded processors’ capabilities, ultra-miniaturized hardware accelerators are being introduced, and the emergence of original and commercial development environments and tools, embedded artificial intelligence/machine learning (AI/ML) technologies have rapidly developed in recent years. At the same time, because … Read more
With the official release of the first RISC-V Chinese book “Hands-On CPU Design – RISC-V Processor Edition” more and more enthusiasts are starting to use the open-source Hummingbird E203 RISC-V core, and many beginners have left messages asking about the use of the RISC-V toolchain. To facilitate beginners in quickly learning RISC-V CPU design and … Read more
Today, I will teach you how to run a RISC-V Linux on the QEMU emulator. A RISC-V Linux includes: opensbi linux root filesystem 1. Download RISC-V Toolchain Downloading the toolchain source code and compiling it can lead to incorrect options, so we will use the precompiled toolchain instead. Website: https://toolchains.bootlin.com This site provides some precompiled … Read more
To gain a deeper understanding of the Linux implementation of the RISC-V 64 architecture, we have specially adapted the Buildroot 2021 open-source build tool, making it easier for everyone to delve into various parts of the Neza D1, such as the boot process, OpenSBI, U-Boot, kernel, root filesystem, etc. Using Buildroot to compile the build … Read more
Corrector: TinyCorrect v0.2-rc2 – [tounix spaces]Author: Chai Zixuan [email protected]: 2024/09/27Revisor: falcon [email protected]: RISC-V Linux Kernel AnalysisSponsor: PLCT Lab, ISCAS This week continues the series of articles on TinyBPT. Remember to bookmark, share, and follow, collection: https://tinylab.org/riscv-linux Zero-threshold transition to RISC-V + Embedded Linux, keep up with TaiXiao Technology’s 30+ lectures on Bilibili, prepare a RISC-V … Read more
“ Corrector: TinyCorrect v0.1 – [codeblock pangu]Author: Kepontry [email protected]: 2022/12/28Revisor: Falcon [email protected], Wang Liming [email protected]: RISC-V Linux Kernel AnalysisProposal: Embedded Linux System for RISC-VSponsor: PLCT Lab, ISCAS ” This week continues the series of articles on embedded RISC-V Linux. Remember to bookmark, share, and follow; write articles to receive subsidies: gitee.com/tinylab/riscv-linux The activity uniformly uses … Read more
Corrector: TinyCorrect v0.2-rc2 – [tounix spaces header]Author: Chai Zixuan [email protected]: 2024/09/27Revisor: falcon [email protected]: RISC-V Linux Kernel AnalysisSponsor: PLCT Lab, ISCAS This week continues the serialization of the TinyBPT series of articles. Remember to bookmark, share, and follow. Collection: https://tinylab.org/riscv-linux Zero-threshold transition to RISC-V + Embedded Linux, follow TaiXiao Technology’s Bilibili open class, prepare a RISC-V … Read more