Click the above blue text to follow us ARM, MIPS, and RISC-V are three common Reduced Instruction Set Computing (RISC) architectures, each with its own characteristics and design philosophies. These architectures are widely used in processor design, but they have essential differences in instruction set structure, development background, and ecosystem. ARM (Advanced RISC Machine): The … Read more
Recently, as an important part of the RuyiSDK RISC-V operating system support plan, RevyOS has successfully added OpenSBI-H based KVM virtualization support for the TH1520 processor platform. This support is based on software virtualization technology, which simulates hardware resources through software, allowing multiple virtual machines to run efficiently on the same physical machine. Preliminary verification … Read more
Vision and Mission of the Jiachen Project Before the next Bingchen year (Dragon Year 2036), based on RISC-V, we aim to establish an open standard system and open-source software stack that covers the entire information industry from data centers to desktop offices, and from mobile wearables to smart IoT. Our goal is to achieve a … Read more
Recently, the Milk-V Duo RISC-V architecture development board has successfully become compatible with the PinPong open-source hardware programming system from Shanghai DFRobot, and it has successfully adapted to many sensors and modules under DFRobot. “Milk-V Duo” is a microprocessor unit (MPU) based on the CV1800B processor, capable of running operating systems based on LINUX and … Read more
The most beautiful April days are coming, and I am excited to announce: a new course will be launched on April 1: Teacher Dongdong from PLCT Lab will bring you “Getting Started with RISC-V: Teacher Dongdong Takes You Through Milk-V Duo“.This is Teacher Dongdong’s first public lecture, please encourage him and provide improvement suggestions.🍻 With … Read more
"IT有得聊" is a professional IT information and service platform under the Machinery Industry Press, dedicated to helping readers master more professional and practical knowledge and skills in the broad field of IT, quickly enhancing their workplace competitiveness. Click the blue WeChat name to quickly follow us! CPU Architecture and Microarchitecture are two important concepts in … Read more
Former RISC-V developers face a challenge: the code density of the RISC-V instruction set for deeply embedded processors lags behind existing ARM Cortex-M tools. However, many new products released by SEGGER are changing this situation, such as the recently released SEGGER Linker, which can reduce the code size of RISC-V by 15%. SEGGER’s Runtime Library … Read more
Introduction to CSR The Control and Status Registers (CSR) of the RISC-V architecture are used to configure or record the operational status of some processor cores. CSR registers are internal registers of the processor core, using a dedicated 12-bit address encoding space, with a maximum of 4096 available. Therefore, accessing CSR registers requires special instructions. … Read more
1. Background Recently, during discussions with some developers or feedback in developer groups, it has been noted that the development approach for the HPM microcontroller is different from traditional microcontroller development methods. Some developers feel lost due to not being familiar with this approach, while others believe their apps heavily rely on hpm_sdk. Based on … Read more
SEGGER Embedded Studio (SES) is a cross-platform integrated development environment (IDE) for ARM and RISC-V architecture processors developed by SEGGER, known for its fast execution speed and strong functionality. SES includes Clang/LLVM and GCC compilers, utilizing SEGGER’s runtime library, which occupies less code space and offers higher execution efficiency compared to GCC’s newlib. SES can … Read more