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ARM, MIPS, and RISC-V are three common Reduced Instruction Set Computing (RISC) architectures, each with its own characteristics and design philosophies.
These architectures are widely used in processor design, but they have essential differences in instruction set structure, development background, and ecosystem.
ARM (Advanced RISC Machine): The origin of ARM dates back to the 1980s, designed by Acorn Computers with the aim of providing high performance and low power processors for personal computers.
With the rise of mobile devices, ARM gradually became the mainstream architecture for smartphones, embedded systems, and Internet of Things devices. ARM adopts a licensing model, allowing chip manufacturers to use its architecture, forming a vast ecosystem.
MIPS (Microprocessor without Interlocked Pipeline Stages): The MIPS architecture is also one of the representative RISC architectures that emerged in the 1980s, originally designed for high-performance workstations and servers.
The MIPS instruction set is relatively simple, suitable for academic research and teaching. Although it has some applications in consumer electronics (such as routers and set-top boxes), its influence on mobile devices is far less than that of ARM.
RISC-V: RISC-V is a relatively new open instruction set architecture, originating around 2010, developed by the University of California, Berkeley.
Unlike the closed licensing models of ARM and MIPS, RISC-V is completely open, allowing anyone to use and extend it for free, providing great freedom for academic research and innovation, and attracting many developers and companies to participate.
ARM supports two main instruction set modes: ARM mode (32-bit instruction length) and Thumb mode (16-bit instruction length).
The Thumb mode can reduce code size and improve memory utilization in embedded systems. Recent ARM architectures (such as ARMv8) also support a 64-bit instruction set (AArch64), expanding the processing capabilities of the processor.
In addition, the ARM architecture introduces some complex features, such as conditional execution and multi-core optimization, which enable ARM to adapt to a wide range of application scenarios.
MIPS is a pure RISC architecture, and its instruction set is very concise, following a “load-store” model, meaning that all data processing operations must be done in registers, with memory access limited to load and store instructions.
The design philosophy of MIPS emphasizes simplifying hardware implementation, reducing the complexity of instruction decoding and execution. MIPS also supports various versions, including 32-bit and 64-bit extensions, but the variety of instructions is relatively limited.
RISC-V has extremely high design flexibility, adopting a modular instruction set architecture, where the core instruction set is minimized, and additional features are implemented through standard extension modules (such as integer multiplication and division, atomic operations, floating-point operations, etc.).
This modular design facilitates the customization of processors for different application scenarios while maintaining standardization. RISC-V is also a “load-store” architecture, supporting various address lengths of 32-bit, 64-bit, and 128-bit, ensuring its scalability.
ARM’s design tends to balance performance and energy efficiency.
It introduces various advanced optimizations, such as a large register set, conditional execution, and Barrel Shifter.
These features can reduce the number of instructions when executing complex algorithms, improving instruction density and energy efficiency.
MIPS emphasizes simplifying processor design, maintaining fewer instruction types and fewer register operations to reduce the complexity of hardware implementation.
Due to its unified and simple instruction set design, MIPS is widely adopted in teaching and research, but its flexibility and efficiency are somewhat lacking in modern high-performance applications.
The original intention of RISC-V’s design is openness, modularity, and scalability. Its concise core instruction set combined with flexible extension modules provides developers with the freedom to customize hardware.
RISC-V also fully considers future scalability, such as supporting a 128-bit address space and dedicated vector processing extensions, making it promising for forward-looking applications.
ARM’s ecosystem is massive, covering a wide range of applications from microcontrollers to high-end servers.
Due to its licensing model, many chip manufacturers (such as Qualcomm, Apple, and Samsung) design their own SoCs (system-on-chip) based on ARM.
The rich ecosystem and broad market support make ARM the preferred choice for mobile computing and embedded development.
Although MIPS has certain applications in consumer electronics and embedded systems, its market share and ecosystem are far inferior to ARM.
In recent years, MIPS has changed hands several times, leading to delays in technology updates and market promotion.
The openness of RISC-V has attracted a large number of developers and startups, making it a popular choice in the field of innovation.
Although RISC-V’s ecosystem is not as mature as ARM’s at present, its rapidly developing open-source community and widespread attention from the industry give it the potential to challenge traditional instruction set architectures.
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