As competition in the microprocessor market intensifies, the RISC-V instruction set has garnered increasing attention. Although RISC-V is not the first open-source Instruction Set Architecture (ISA), it is the first ISA that allows flexible selection of instruction sets based on actual application scenarios. The RISC-V architecture can accommodate all application scenarios, from high-performance server CPUs … Read more
Real-Time Memory Management Enhances Memory Operation Efficiency Segger Embedded Studio for RISC-V recently updated to version v6.22a, utilizing real-time memory management technology. This technology improves the efficiency of memory allocation and deallocation, reducing response time and meeting the hard real-time requirements for applications written in C++. The new version supports all common 32-bit and 64-bit … Read more
According to a report from Electronic Enthusiasts Network (by Huang Jingjing), with the continuous advancement of hardware and software technologies, the application of embedded systems in industries such as automotive, industrial automation, medical, and the Internet of Things is becoming increasingly widespread. These industries exhibit significant market size and growth rates. In a recent interview … Read more
Recently, foreign media reported that MIPS Technologies announced it would abandon the design of the MIPS instruction set and shift to RISC-V. In response, Tieliu couldn’t help but sigh, “Forty years east of the river, forty years west of the river“. MIPS, as the first commercially available RISC instruction set, has been abandoned by the … Read more
The report from Electronic Enthusiasts (by Electronic Enthusiasts) states that 38 years ago, an innovative RISC ISA was born at Stanford University in the United States, leading to the emergence of MIPS. With this project, several founders established MIPS Corporation, which successively launched the R2000 and R3000 microprocessors in the 1980s. Because of this, MIPS … Read more
In fact, MIPS has long been dead, merely maintaining vital signs through an external circulatory system. The external circulatory system of MIPS consists of former MIPS chip design companies, such as Loongson’s desktop and server CPUs and Junzheng’s mid-to-high-end embedded CPUs. They only use the MIPS instruction set, while the CPU cores are entirely independently … Read more
RISC-V and ARM are both processor architectures based on the RISC (Reduced Instruction Set Computer) principle, but they have significant differences in design philosophy, business models, openness, ecosystems, and application scenarios. Here are the main differences between the two: 1. Architecture Openness RISC-V Open Source Instruction Set Architecture (ISA): The instruction set specification of RISC-V … Read more
According to a report by Electronic Fan Network (by Zhou Kaiyang), the rapid increase in the number of MCUs within a single vehicle has provided a new opportunity for IC design companies. Many MCU manufacturers that previously focused on consumer electronics are now pivoting towards automotive electronics.However, for any automotive chip manufacturer, truly entering the … Read more
[Hsinchu, Taiwan] — October 12, 2022 — Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of 32/64-bit, high-performance, and low-power RISC-V processor cores and a founding member of the RISC-V International Association, today announced that Renesas Electronics Corporation (TSE: 6723), a globally recognized advanced semiconductor solutions provider, has adopted Andes Technology’s entry-level … Read more
1. Use Emulators QEMU: Supports RISC-V and can run RISC-V operating systems and programs (such as Ubuntu, Fedora, etc.). qemu-system-riscv64 -machine virt -nographic \ -m 8192 -smp 4 -kernel /usr/lib/u-boot/qemu-riscv64_smode/uboot.elf \ -device virtio-net-device,netdev=eth0 \ -netdev user,id=eth0,hostfwd=tcp::6666-:22 \ -device virtio-rng-pci -drive \ file=./ubuntu-24.04.1-preinstalled-server-riscv64.img,format=raw,if=virtio Spike (Official RISC-V Emulator), the official emulator provided by the RISC-V Foundation, suitable … Read more