Today, a customer asked us whether the programming speed of our SOP8 Flash chip would increase if the QE=1 setting is applied. Let us revisit the concept of SPI Flash chips. SPI FLASH typically supports the following communication modes: Standard SPI (Single/Dual/Quad) 1. Single SPI (Single Line Mode): Uses IO0 (MOSI) to send data, IO1 … Read more
In this article, we learned how to customize Linux using PetaLinux and created a boot file for the SD card. This issue introduces how to configure PetaLinux to generate a Linux image file that boots from QSPI Flash. Copying the PetaLinux Project If we want to keep the PetaLinux project that boots from the SD … Read more
Little_flash—— is the SPI Flash driver library for LuatOS, which mounts SPI Flash as an lfs file system, supports NAND/NOR Flash, and provides a unified API to simplify device storage expansion and driver development. This article will take theAir780EHM core board as an example to share an application example of Little_flash. Using the Air780EHM core … Read more
SPI Flash is a type of non-volatile memory chip based on the Serial Peripheral Interface (SPI) protocol, featuring numerous significant advantages that make it widely used in various electronic devices. Compact Size: SPI Flash chips utilize advanced packaging technology, resulting in a small size that effectively saves circuit board space, enabling the miniaturization of products. … Read more
This is a fundamental choice that affects system architecture, performance, cost, and reliability. To better understand the core differences, we can use a metaphor: eFlash MCU is like a laptop with a massive built-in solid-state drive (SSD). All data and the operating system are directly integrated on the motherboard, providing extremely fast access, ready to … Read more
“ This article focuses on the ESP32-S3, explaining its SPI Flash partition table settings, connection to Flash, and also introduces partition table configuration and initialization mounting of each partition.” 01 — Introduction 1. The Partition Table of ESP32-S3 (Partition Table) is a configuration mechanism used to divide the SPI Flash storage space. Its function is … Read more
1. Introduction The XCZU9EG core board uses the Xilinx Zynq UltraScale+ MPSoCs EG series FPGA as the main control chip, model XCZU9EG-2FFVB1156I. The physical image of the core board is shown in Figure 1.1: Figure 1.1 Physical image of the XCZU9EG core board This core board integrates 6 Micron DDR4 chips (model: MT40A512M16LY-062E), with 4 … Read more