Choosing Between SPI Flash and eFlash MCUs: A Comprehensive Guide

This is a fundamental choice that affects system architecture, performance, cost, and reliability. To better understand the core differences, we can use a metaphor:

• eFlash MCU is like a laptop with a massive built-in solid-state drive (SSD). All data and the operating system are directly integrated on the motherboard, providing extremely fast access, ready to use, and more secure and robust. However, upgrading the hard drive is very difficult.

• SPI Flash MCU is like a laptop with very limited built-in storage but with a high-speed SD card slot. The operating system and programs are stored on the SD card. The computer needs to load the system from the SD card into memory to run. You can replace the SD card with a larger capacity at any time, but the speed will be slower than the built-in SSD, and the SD card may be removed or damaged.

1. Differences in Core Architecture and Operating Principles

This is the root of all differences.

1. eFlash MCU (Embedded Flash MCU)

• Architecture: The flash memory is integrated as an IP core directly on the same chip die as the MCU’s CPU core, SRAM, peripherals, etc.

• Process: Typically uses a mixed process or specially optimized process nodes (such as 40nm, 55nm eFlash), allowing logic transistors and Flash storage cells to be manufactured under the same process.

SPI Flash MCU

• XiP (eXecute in Place): Maps external SPI Flash to the MCU’s address space, allowing the CPU to read and execute directly. However, it is slow and heavily relies on cache.

• Load to RAM for Execution: After powering on, a built-in Bootloader copies the code from SPI Flash to internal SRAM, then executes at full speed from SRAM. This requires the MCU to have sufficiently large SRAM.

• Architecture: The MCU itself (usually using more advanced or economical pure logic processes, such as 28nm, 22nm) contains only the CPU, SRAM, and peripherals. The program is stored in a separate, external SPI interface Flash chip.

• Process: The MCU and Flash are manufactured, packaged, and tested using two completely different processes. SPI Flash uses a dedicated process optimized for its storage cells.

2. Comparison Dimensions

1. Performance

• eFlash MCU: High Performance

• Zero Wait-State: eFlash connects directly to the core via a wide internal bus (such as 128-bit, 256-bit), acting as the CPU’s “local hard drive,” enabling the most efficient instruction fetching and data access, especially for random access.

• No Code Loading Process Required: Executes immediately after power-on, resulting in fast startup speeds.

• SPI Flash MCU: Performance Bottleneck

• XiP (eXecute in Place): Executes directly from external Flash, simple and cost-effective, but slow, especially for non-sequential code (with branch jumps), requiring frequent caching (Cache), and cache misses can significantly impact performance.

• Load to RAM for Execution: After powering on, the code is copied from SPI Flash to internal SRAM for execution. This requires the MCU to have sufficiently large SRAM and increases startup latency.

• Bandwidth Limitations: The bandwidth of the SPI interface (even Quad-SPI) is far lower than that of the MCU’s internal bus. It is like the CPU’s “USB 2.0 external hard drive.”

• High Latency: Each access incurs communication overhead (instruction and address transmission).

• Execution Method:

Conclusion: eFlash MCU outperforms in performance, suitable for high-speed real-time applications.

2. Cost

• eFlash MCU: High Unit Chip Cost

• Integrating Flash into advanced logic processes is a complex and expensive technology. The eFlash module increases the die size of the chip, especially in mature processes (such as 40nm and above), where the eFlash unit may be significantly larger than the logic unit, greatly increasing costs.

• SPI Flash MCU: Low Unit MCU Cost, but System Cost Needs Assessment

• The MCU uses pure logic processes (such as 28nm, 16nm), without the expensive eFlash, resulting in a smaller die size and lower cost.

• Requires additional procurement of SPI Flash chips or dies, increasing material count, PCB area, and assembly/testing costs.

Conclusion: For mass production, the total system cost of the eFlash solution may be more advantageous. For small storage needs, the SPI Flash solution may be cheaper, as it allows for the selection of less expensive small-capacity MCUs and SPI Flash.

3. Reliability and Security

• eFlash MCU: High Reliability, High Security

• Code is stored internally on the chip, making it difficult to steal via physical probing.

• It is easier to implement complete hardware security features, such as secure boot, encryption engines, write protection, and lifetime management (OTP area), all within a secure chip.

• Reliability: Single-chip solution reduces external connections and solder points, providing better resistance to vibration and electromagnetic interference, making it more suitable for harsh environments like industrial and automotive (AEC-Q100 certified).

• Security:

• SPI Flash MCU: Lower Reliability, Higher Security Risks

• Reliability: The wire bonding between the internal SPI FLASH and the MCU die is a potential failure point.

• Security: Although SPI Flash can be encrypted, the keys and decryption process still reside in the MCU, and plaintext data on the bus remains at risk.

Conclusion: eFlash MCU has a natural advantage in reliability and security.

4. Design Complexity and Flexibility

• eFlash MCU: Simple Design, Low Flexibility

• Simple Design: No need to design external memory circuits, simple wiring. No need to consider code relocation, XiP mapping, etc. in software.

• Low Flexibility: Flash capacity is fixed at the time of chip manufacturing and cannot be upgraded later. Different capacities require selecting different MCU models.

• SPI Flash MCU: Complex Design, High Flexibility

• Complex Design: Requires adding an additional chip. Software needs to configure XiP or write a Bootloader for code loading.

• High Flexibility: Can flexibly choose different capacities (from 1Mb to 1Gb+) and different models of SPI Flash according to project needs, and even upgrade program capacity by replacing Flash chips after product release.

Conclusion: The SPI Flash solution offers great flexibility in capacity selection but increases hardware and software development complexity.

5. Process Nodes and Capacity

• eFlash MCU: Relatively Outdated Process, Limited Capacity

• Integrating eFlash into advanced logic processes (such as <28nm) is very difficult and costly. Therefore, most MCUs with eFlash remain at mature process nodes like 40nm, 55nm.

• Capacity is usually within a few MB (commonly 256KB~2MB), with very few exceeding 4MB.

• SPI Flash MCU: Advanced MCU Process, Large Flash Capacity

• The MCU can use the most advanced logic processes (such as 22nm, 16nm), achieving extremely high clock speeds and very low power consumption.

• External SPI Flash can use proprietary Flash processes, allowing for very large capacities (from Mbit to Gbit levels) at a cost-effective price.

Conclusion: For applications requiring ultra-large program storage or using the most advanced processes (such as AIoT), SPI Flash is the only choice.

3. Summary and Selection Guide

Choose eFlash MCU when your project:

• Pursues high performance and real-time capabilities: For example, motor control, digital power, high-speed sensor processing, etc.

• Operates in harsh environments: For example, automotive electronics, industrial control, aerospace, requiring high reliability and stability.

• Security is a primary consideration: Involving payment, identity authentication, encrypted communication scenarios.

• Code size is moderate and fixed: Typically less than 4MB.

Choose SPI Flash MCU when your project:

• Requires ultra-large program or data storage: For example, graphical user interfaces (GUI), audio files, video buffering, machine learning models.

• MCU requires extreme performance or power efficiency: Desiring to use the most advanced process MCU cores (such as Cortex-M7/A series high-frequency chips).

• Needs flexibility: Product lines need to cover different storage capacities, or storage size may need to be adjusted in the later design phase.

Hybrid Solutions (Common in High-End Applications):

Many modern MCUs adopt a compromise solution:internally integrating a small amount of eFlash for storing secure boot code (BootROM) and critical programs, while providing a QSPI interface for connecting large-capacity Flash for storing main application programs and data. This ensures both startup speed and security while gaining storage capacity and flexibility.