As the applications of SoC and FPGA continue to expand in artificial intelligence, automotive electronics, 5G communications, and edge computing, the design complexity of the Power Distribution Network (PDN, Power Distribution Network) has significantly increased.
The requirements for multiple voltage rails, transient response, and strict voltage accuracy have made power design not just a peripheral concern, but a critical factor determining system performance and stability.
The following content summarizes the key points that engineers need to pay special attention to in the power design of SoC and FPGA.
01
Clarify Power Requirements: Multiple Voltage Rails and Their Characteristics
A typical SoC or FPGA requires the following voltage rails:
- Core Voltage (Vcore): High current, low voltage (e.g., 0.9V~1.2V), with high accuracy requirements;
- Analog Voltage (Vana): Sensitive to noise and ripple, typically 1.8V or 2.5V;
- I/O Voltage (VIO): 1.5V/1.8V/3.3V, used for peripheral interfaces;
- Auxiliary Voltage (Vaux): Drives PLL, peripherals, and control units.
🔎Notes::
- The current differences between different voltage rails need to be evaluated separately for load capacity;
- The voltage timing requirements must be adhered to, otherwise it may lead to SoC/FPGA power-up failures;
- Power supply noise directly affects logic stability and signal integrity.
02
DC Accuracy (Static Error) Control
The main factors affecting DC accuracy are:
- Reference Voltage Accuracy (Vref)
- Voltage Divider Resistor Tolerance
- Load/Line Regulation
- PCB Trace Voltage Drop (DC Losses)
âš¡Engineer Recommendations::
- Select high-precision reference sources and 0.1% precision resistors;
- Use Remote Sense, with feedback directly connected to the power pins of FPGA/SoC;
- Place power chips as close to the load as possible, using wide copper and short traces to reduce voltage drop.
03
AC Accuracy (Dynamic Error) and Transient Response
Transient current changes (e.g., when many logic units in FPGA switch simultaneously) can lead to voltage overshoot/undershoot. Influencing factors include:
- Load Change Rate (dI/dt);
- Power Control Topology (voltage mode, current mode, DCS control, etc.);
- Selection and layout of output inductors and capacitors.
âš¡Engineer Recommendations::
- Select DC/DC converters with internal compensation (e.g., TI TPS62000 series) to reduce debugging complexity;
- Appropriately increase output capacitance to improve transient absorption capability, but ensure stability;
- Pay attention to inductor saturation current to avoid failure under transient conditions.
04
Power Architecture Selection
Common intermediate voltage rails include:12V, 5V, 3.3V.
- 12V: Low input current, but low efficiency;
- 5V: Higher efficiency, moderate input current;
- 3.3V: Highest efficiency, but maximum current and fewer device options.
âš¡Engineer Recommendations::
- Select intermediate rails based on the system power supply environment, evaluating the balance of efficiency – current – device availability;
- For high-performance FPGA, use discrete power supplies (one rail, one power supply) for more flexibility;
- For low-power applications, consider PMIC integrated solutions to simplify design and timing control.
05
Light Load Efficiency and Mode Switching
Many power chips support PFM (Pulse Frequency Modulation) power-saving mode, enhancing efficiency under light load. However, the downside is that ripple and DC error may increase, potentially failing to meet the strict accuracy requirements of FPGA.
âš¡Engineer Recommendations::
- Prioritize power devices that support forced PWM mode;
- Avoid using only PFM mode on the FPGA power rail to prevent stability issues.
06
Testing and Verification Key Points
- Voltage waveforms should be measured at the FPGA pins, not at the power output;
- Test dynamic current waveforms to assess whether overshoot/undershoot amplitudes meet the ±5% requirement;
- Verify power-up timing to avoid configuration failures of FPGA due to power delays or voltage drops.
Summary
The complexity of power distribution design for SoC and FPGA far exceeds that of traditional MCU. Engineers must carefully weigh considerations in multiple voltage rail management, DC/AC accuracy, transient response, architecture selection, and light load mode control.
In summary:👉Power design is not just about “power supply”, it is a key weapon to unleash the performance of SoC/FPGA.
