Table of Contents 1. GPIO Interrupt Related Registers 2. Code Implementation of PA1 Input Interrupt 3. Summary & Precautions 01 — GPIO Interrupt Related Registers In the previous STM32 series tutorial (3): Understanding STM32’s GPIO, several basic registers of GPIO were discussed. However, to use the interrupt functionality, it is necessary to utilize the GPIO … Read more
Part.0 Introduction: Why Do We Need Interrupts? Imagine you are reading a book at home, but you also need to pay attention to visitors. At this moment, you have two options: Polling: Every few minutes, you put down the book to check at the door if someone is there – this is inefficient and prevents … Read more
If you ask me what the most persistent issue in embedded development is, I would say just two words: interrupts. Especially in STM32, if the interrupt priorities are not configured correctly, the system may appear normal on the surface, but underneath it is a complete mess. The loss we experienced was a vivid example. It … Read more
Click the blue text above to follow us Embedded Training – Choose Jufeng Smart Link STM32 interrupt priority mechanism is a concept that often confuses beginners and newcomers to projects. What is preemption? What is response priority? What is the purpose of priority grouping? Why does the priority you set not take effect at all?Don’t … Read more
The Cortex-M3 and Cortex-M4 processors utilize a 32-bit architecture, with internal registers in the register set, a 32-bit data path, and bus interfaces, employing Thumb-2 technology that supports both 16-bit and 32-bit instructions. They feature the following characteristics: Three-stage pipeline design Harvard bus architecture (I-BUS, D-BUS) 32-bit addressing AMBA bus interface NVIC interrupt controller, supporting … Read more
The Cortex-M0 is part of the M0 series within the Cortex-M family. Its main feature is a low-power design. The Cortex-M0 is a 32-bit, 3-stage pipeline RISC processor, with a core architecture based on the von Neumann structure, meaning that instructions and data share the same bus. As a next-generation processor, the design of the … Read more
In embedded development, handling asynchronous events is an unavoidable challenge. For instance, reading sensor data from an accelerometer to calculate steps, or triggering RTOS context switches via timers, all rely on the support of exception handling mechanisms. Today, we will discuss the exception handling model of ARM Cortex-M. The Core of Exception Handling In the … Read more
Today, we will discuss interrupt handling in ARM Cortex-M. In embedded systems, interrupts are the core mechanism for achieving real-time responses. Imagine if there were no interrupts: • When a button is pressed, the system might be busy with other tasks and miss the response. • Incoming communication data might be lost due to untimely … Read more
Reminder: This article briefly reviews the relevant knowledge points of EXTI and NVIC, analyzing the external interrupt callback mechanism of the STM32F1 series microcontroller. Before we start, let’s review some knowledge related to EXTI and NVIC: External Interrupt/Event Controller (EXTI) For interconnect products (series 105, 107), the external interrupt/event controller consists of 20 edge detectors … Read more
Reminder: This article takes external interrupt for lighting as an example, analyzing the usage of interrupt service related functions in the HAL library, their interconnections, and underlying principles. 1. Example Implementation Example Overview: The main function controls LED2 to blink, while the interrupt controls the switch of LED0: First, we use CubeMX to create the … Read more