The Cortex-M3 and Cortex-M4 processors utilize a 32-bit architecture, with internal registers in the register set, a 32-bit data path, and bus interfaces, employing Thumb-2 technology that supports both 16-bit and 32-bit instructions. They feature the following characteristics:
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Three-stage pipeline design
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Harvard bus architecture (I-BUS, D-BUS)
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32-bit addressing
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AMBA bus interface
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NVIC interrupt controller, supporting up to 240 interrupt requests and 8-256 interrupt priorities
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Support for various OS features, such as tick timers and shadow stack pointers
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Sleep mode and low power consumption
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MPU
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Bit-field features (support for bit data access in two specific memory regions)
Instructions:
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General data processing: + – x ÷
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Memory access instructions
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Bit-field processing instructions
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Multiply-accumulate and saturation instructions
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Instructions for jumps, conditional jumps, and function calls
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System control instructions that support OS
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Single Instruction Multiple Data (SIMD)
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Floating-point instructions
ARM primarily provides:
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Design of units such as logic gates and memory
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Peripherals and AMBA basic components (Cortex-M System Design Kit CMSDK, ARM Corelink)
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Other debug components for connecting debugging systems in multiprocessor designs (ARM Coresight IP)
Thumb ISA Architecture
Since the processor supports both 16-bit and 32-bit instructions in the Thumb-2 instruction set, there is no need to switch between Thumb state (16-bit instructions) and ARM state (32-bit instructions). According to the Thumb-2 encoding, if the [15:11] bits are encoded as 0b11101, 0b11110, or 0b11111, then it is a 32-bit instruction.
