UT Verification of SPI Function in USI Module of WUJIAN100

UT Verification of SPI Function in USI Module of WUJIAN100

Recently, I spent some time organizing the verification of the SPI module in the USI module of the WUJIAN100 project. Here, I would like to share some of my thoughts and methods. Basic Introduction to the Design Functionality of the USI Module USI (Unified Serial Interface) is a combined module that includes UART, SPI, and … Read more

Chip Tape-out Success Rate Plummets to 14%: The Technical Winter Behind the Failure of Eight Out of Ten Design Companies

Chip Tape-out Success Rate Plummets to 14%: The Technical Winter Behind the Failure of Eight Out of Ten Design Companies

A precise maze on a wafer is consuming billions in R&D funds and market opportunities. In June 2025, the semiconductor industry faced a silent “avalanche.” According to the latest data from Siemens EDA: the global chip tape-out success rate has plummeted to a historic low of 14%, meaning that eight out of ten design companies … Read more

Chip Industry Faces Challenges: First Tape-Out Success Rate Drops to Just 14%

Chip Industry Faces Challenges: First Tape-Out Success Rate Drops to Just 14%

The chip industry has recently been hit with concerning news: data from electronic design automation tools released by Siemens indicates that the current success rate for first tape-outs has plummeted to an unprecedented low of 14%. Just two years ago, this figure was around 24%, meaning the failure rate has surged by ten percentage points … Read more

Siemens EDA: First Tape-Out Success Rate Drops to 14% in 2024!

Siemens EDA: First Tape-Out Success Rate Drops to 14% in 2024!

On May 14, according to EEnews Europe, Abhi Kolpekwar, Vice President and General Manager of Siemens EDA’s Design Verification Technology, stated that the first tape-out success rate (referring to chips based on advanced process technology) is currently declining, having dropped from 32% in 2020 and 24% in 2022 to 14% in 2024. “This is a … Read more

Chip Yield Rate Halved! 3D Packaging Triggers the Most Severe Technological Crisis in Two Decades

Chip Yield Rate Halved! 3D Packaging Triggers the Most Severe Technological Crisis in Two Decades

Have you ever touched a freshly baked smartphone chip? That silicon wafer the size of a fingernail is now a hot potato. According to Siemens EDA’s latest data, the global chip yield rate has halved for the first time—plummeting from 24% two years ago to just 14% now, more shocking than your child’s declining monthly … Read more