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Siemens EDA: First Tape-Out Success Rate Drops to 14% in 2024!

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Siemens EDA: First Tape-Out Success Rate Drops to 14% in 2024!

On May 14, according to EEnews Europe, Abhi Kolpekwar, Vice President and General Manager of Siemens EDA’s Design Verification Technology, stated that the first tape-out success rate (referring to chips based on advanced process technology) is currently declining, having dropped from 32% in 2020 and 24% in 2022 to 14% in 2024. “This is a … Read more

Chip Yield Rate Halved! 3D Packaging Triggers the Most Severe Technological Crisis in Two Decades

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Chip Yield Rate Halved! 3D Packaging Triggers the Most Severe Technological Crisis in Two Decades

Have you ever touched a freshly baked smartphone chip? That silicon wafer the size of a fingernail is now a hot potato. According to Siemens EDA’s latest data, the global chip yield rate has halved for the first time—plummeting from 24% two years ago to just 14% now, more shocking than your child’s declining monthly … Read more