On May 14, according to EEnews Europe, Abhi Kolpekwar, Vice President and General Manager of Siemens EDA’s Design Verification Technology, stated that the first tape-out success rate (referring to chips based on advanced process technology) is currently declining, having dropped from 32% in 2020 and 24% in 2022 to 14% in 2024.
“This is a surprising and shocking decline in both ASIC and FPGA,” said Abhi Kolpekwar. “This is a very significant issue, and the reasons can be traced back to the design complexity of current customer tape-outs.”
Siemens EDA has developed a set of interlocked tools for using AI agents to verify designs in an attempt to address this issue.
“The second issue is timing constraints. 75% of projects are behind schedule. Then, skilled engineers can only meet 20% of the requirements, so currently, 80% of the requirements are unmet,” Abhi Kolpekwar stated. “My business is to help people verify the functionality of their designs before tape-out, to discover any errors in the design as early as possible. The longer errors stay in the system, the more costly they become, so the plan is to capture as many as possible as early as possible, so people do not have to redesign.”
“Simply producing faster simulators is not enough. We need faster engines, faster engineers (through automation of tasks and analysis), and less workload. All of this increases the overall productivity of the end user by five times,” Abhi Kolpekwar said.
Currently, Siemens EDA has launched Questa One, which features three elements: a new simulation engine, verification tools, and verification IP, all utilizing generative AI and AI agents. These tools are being used by ARM, Mediatek, Rambus, and Microsoft.
For example, the intelligent creation tool takes design requirements and transforms them into design specifications for formal verification using Generative AI. The intelligent regression tool identifies failure modes and quickly debugs issues using predictive AI.
“You do not need to run thousands of regression tests; just run a few hundred optimization tests for any design changes. Additionally, it can predict which test cases are likely to fail and prioritize them, so if a regression fails, you do not have to run the rest of the tests,” Abhi Kolpekwar said. “This is how we use AI to reduce workload.”
The intelligent engine can access all design databases and testing platforms to accelerate data computation and simulation, while the intelligent debugging tools use AI to identify faults and provide root cause analysis for specific code.
Siemens EDA has developed a new simulation engine that supports parallel simulation with automatic partitioning, functional safety simulation, and static and dynamic power analysis.
Before delivery to customers, AI is trained based on standard documentation in Siemens EDA, and the model will be trained using a locally trained model with retrieval-augmented generation (RAG). This simplifies the verification toolchain.
“You can use generative AI code generation for test benches or to run formal checkers, but that is not enough,” Abhi Kolpekwar said. “You can select parts from the design requirement document and generate results directly from the document.”
Another part of the QuestaOne verification toolchain is the Stimulus-Free Verification (SFV), which discovers errors without the need for a simulation platform for static and formal verification.
“The idea of SFV is to combine GenAI, LLM, predictive, and analytical AI for static and formal analysis, rather than starting the linter where the user poses questions; we apply the linter, find violations, and automatically fix them, then run RTL to TRL equivalence checks,” Abhi Kolpekwar said.
The Verification IQ tool uses analytical AI and generative AI to automate tasks and workloads. This comes from Siemens EDA’s acquisition of Avery Design Systems in 2023.
Abhi Kolpekwar stated, “We are building this benchmark protocol technology, introducing the infrastructure for test cases and AI applications through the verification IP ecosystem. Since we acquired them, we have created a verification IP ecosystem with simulatable and emulatable IP on QEMU software simulation and Veloce hardware simulation.” The applications range widely from automotive and AI accelerator chips to storage devices and aerospace design.
“Our customers provide feedback on how to accelerate complex design speeds, automate tasks to complete tasks faster, and help design verification managers save resources,” Abhi Kolpekwar said.
“The Questa One intelligent verification solution has improved our verification efficiency in traditional local and cloud deployments,” said Karima Dridi, Director of Productivity Engineering at Arm. “As an early adopter running large EDA workloads using the high-performance Questa One Sim advanced feature simulator, we have observed improvements in performance, cost-effectiveness, and reduced regression time with the latest AArch64 architecture.”
Chienlin Huang, Senior Technical Manager of the IoT Technology Department at Mediatek, stated, “As an early influencer of Siemens Questa One intelligent verification solution, Mediatek has been able to leverage formal verification and simulation technology to enhance our engineers’ productivity throughout the verification process. The Questa One Property Assist has saved us weeks of engineering time using generative AI, while the Questa One Regression Navigator can predict which simulation tests are most likely to fail, running them first and saving days of regression and debugging time.”
“The Questa One DFT (QDX) simulation utilizes advanced DFT-centric simulation capabilities, providing faster performance than existing simulation solutions, reducing our verification time from weeks to days,” said Claudia Muia-Tartevet, DFT Director at Microsoft. “In addition to these impressive accelerations, QDX also provides up to 20% performance improvement on Microsoft’s Azure Cobalt 100 platform, releasing higher efficiency for our EDA workloads.”
Susheel Tadikonda, Vice President of Silicon IP Engineering at Rambus, stated, “Siemens’ Questa One intelligent verification improves and simplifies our verification process, enabling us to handle next-generation data center workloads such as generative AI with state-of-the-art silicon IP solutions for PCIe, CXL, and HBM interfaces. Utilizing the complete Questa One solution, including simulation, static and formal analysis, and verification IP technology, enhances customer confidence through comprehensive verification of IP solutions for SoC and small chip designs.”
Source | Chip Intelligence
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