Recently, I spent some time organizing the verification of the SPI module in the USI module of the WUJIAN100 project. Here, I would like to share some of my thoughts and methods.
Basic Introduction to the Design
Functionality of the USI Module
USI (Unified Serial Interface) is a combined module that includes UART, SPI, and I2C. In addition to the protocol interfaces of these three modules, it also contains three sets of interfaces: APB, DMA, and interrupts. While the USI is operational, the functionality of the USI and the values of the control registers within it cannot be changed; otherwise, data may be lost. Changes can be made when the USI module is disabled.
SPI Module
The SPI module can be configured in two modes: master and slave. It supports optional configurations for nss, cpol, cpha, and tmod functionalities, as well as the configuration of data_size for data transmission length.
Verification Environment
Using a UVM verification environment, combined with SVT_APB_VIP and SVT_SPI_VIP, to complete the register configuration and data transmission for SPI.
Environment Structure
The integration of APB VIP and SPI VIP refers to tb_apb_svt_uvm_basic_ral_sys and tb_spi_svt_uvm_basic_1m_1s_sys, respectively.
Register Model Generation
Organize register information into a script-supported Excel format and generate the register model.
Test Case Writing
The test cases in the environment mainly use testcase to call the virtual sequence, which then calls the reg sequence for register model operations and the sequence for SPI VIP.
Simulation Waveform
More specific implementation details will be updated in the community later. Interested individuals can join the community for further discussion and learning.
