Multiple failed tape-outs may lead to the collapse of a company.
The chip industry is no stranger to tape-out.
The so-called tape-out refers to the process of manufacturing chips through a series of steps, akin to an assembly line. This stage is crucial as it lies between chip design and mass production. In simple terms, it involves handing over the designed solution to a chip manufacturing plant to produce a few samples for testing whether the designed chip works, followed by optimization. If the tests are successful, large-scale production begins. Therefore, to test whether the integrated circuit design is successful, tape-out is essential. This is also a significant reason why chip design companies need to invest heavily in the early stages. The tape-out process is a critical step from design to mass production. Once the chip is fully designed, it needs to be etched onto the wafer according to the blueprint. The choice of process technology, the size of the wafer, and the complexity of the chip all affect the success rate and cost of tape-out. Moreover, many chips do not succeed in tape-out on the first attempt; often multiple tape-outs are required to achieve satisfactory results.
However, tape-out is a very costly endeavor. A few failed tape-outs may lead to the collapse of a company. In 2019, there were reports of Xiaomi’s Pinecone Electronics experiencing five consecutive tape-out failures with their Pangu S2 series chips, resulting in a painful restructuring of the design team. Some major chip manufacturers have calculated that for a 14nm process chip, a single tape-out costs around $3 million; for a 7nm process chip, it costs about $30 million; and for a 5nm process chip, it can reach as high as $47.25 million.
It is evident that tape-out represents a significant expense for chip design companies, especially for small and medium-sized enterprises in the industry, where the actual tape-out costs are much higher than those of larger firms, exacerbating their already limited financial resources.
01.Why is tape-out so expensive?
So, why is the price of chip tape-out so high?
This brings us to the principles of chip manufacturing. Chip manufacturing involves placing billions of transistors within a very small chip, and the manufacturing process has reached the nanometer level, requiring photolithography to complete the task. Photolithography uses masks (also known as photomasks) to project the desired patterns onto the wafer. The high cost of tape-out is partly due to the need to validate many processes at the outset. From a circuit diagram to a chip, every step must be verified for feasibility, and the circuit must meet the required performance and functionality. The tape-out process lasts at least three months (including material preparation, photolithography, doping, electroplating, packaging, and testing), generally involving over 1,000 process steps, making it the most critical and costly phase of chip manufacturing. If the tape-out is successful, large-scale chip production can commence; otherwise, the reasons for failure must be identified, and corresponding design optimizations must be made. The primary costs associated with tape-out are the masks and wafers, both of which are expensive consumables, with masks being the most costly. A set of mid-range process masks costs about $500,000, while a single wafer can cost several thousand dollars.
02.Which is more expensive, the mask or the wafer?
The mask is made of quartz and serves as a tool for transferring patterns during the microelectronics manufacturing process, similar to a traditional camera’s film. Based on the required patterns, photolithography is used to engrave micron and nanometer-level fine patterns onto the mask substrate, which carries the design and process technology content. The process of transferring the mask’s patterns onto the wafer can be likened to the workflow of a banknote printing machine. The photolithography machine is akin to the printing press, the wafer is like the banknote paper, and the mask is the printing plate, which prints the banknote’s design onto the paper, just as the photolithography machine prints the chip design from the mask onto the wafer.
▲ Working principle of photolithography
The quality of the mask directly affects the quality of photolithography. Manufacturing defects and errors on the mask can be introduced into the chip manufacturing process through photolithography. Therefore, the mask is one of the determining factors for the precision and quality of downstream products. The price of the mask primarily depends on the “process node” chosen for the chip. The higher the process node, the more expensive the tape-out. This is because more advanced process nodes require more layers of masks. It is understood that for a 14nm process, about 60 masks are needed, while for 7nm, it may require 80 or even over a hundred masks. The increased number of mask layers not only raises the cost of the masks but also necessitates additional photolithography steps, requiring more application of photoresist, more exposure, and more development, significantly increasing the overall costs. According to IBS data, the mask costs for 16/14nm processes are around $5 million, while for 7nm processes, the mask costs rapidly rise to $15 million.
▲ The mask cost for 7nm processes is approximately $15 million (Source: IBS)
The overall cost of the mask includes the costs of quartz, photoresist, and other raw materials, as well as the usage costs of Mask Writers and Inspection equipment, along with the costs associated with generating mask-related data, including software licenses for OPC, MDP, server usage, and labor development costs. For a single chip, masks can easily exceed dozens of layers, requiring numerous steps, equipment, software, and personnel, which naturally leads to high costs. In the tape-out phase, the cost of the mask accounts for a significant portion, as the initial tape-out stage involves producing 5-25 pieces for product validation, with the primary cost being the mask. In contrast, during formal production, the mask cost is only counted once, and the subsequent large number of wafers can share the cost, making it cheaper. More accurately, the cost averaged over each chip decreases, rather than the total tape-out cost decreasing. Industry insiders reveal that the tape-out cost for a certain foundry at 40nm is approximately $600,000 to $900,000, with the mask accounting for a significant portion, around $600,000 to $900,000; the wafer cost is about $3,000 to $4,000 per piece. Therefore, if 10 wafers are produced, the cost per wafer is ($900,000 + $4,000 * 10) / 10 = $94,000; however, if 10,000 wafers are produced, the cost per wafer is ($900,000 + $4,000 * 10,000) / 10,000 = $4,090. It is evident that once mass production begins, producing tens of thousands of wafers can bring the cost per wafer down to around $3,000 to $4,000, significantly reducing the mask cost per wafer. Thus, during the small tape-out phase, the mask cost is the primary expense, while in mass production, the wafer cost dominates. Additionally, semiconductor manufacturing equipment can cost millions of dollars, with some exceeding $100 million. It is understood that a mask machine for 28nm costs over $50 million. These machines typically have a depreciation period of seven years. This means that approximately 14% of the machine’s value is lost after just one year of use. The depreciation period for equipment in the wafer foundry industry is usually 5-7 years. Reports indicate that SMIC’s depreciation expenses exceeded 1.4 billion in 2019, primarily due to the need to purchase high-priced machinery for advanced processes, leading to increased depreciation costs year by year. TSMC’s depreciation expenses in 2021 reached nearly 100 billion New Taiwan dollars, setting a record high. From the perspective of process development cycles, the costs and depreciation of machines are already very high, but achieving yield and reliability that meet mass production requirements is also a challenging task. (It is reported that a certain factory’s 28nm machines were all in place by 2011/2012, but even after 5-6 years, the yield had not reached strict mass production standards, highlighting the difficulty. Meanwhile, they incurred significant losses in equipment depreciation over the years.) Furthermore, there are labor costs, maintenance costs, and consumable costs, all contributing to the high mask costs. According to etnews, with the current deterioration of supply and demand conditions, mask prices are rising, and delivery times are being delayed. Even with additional payments, it is challenging to purchase them promptly. The usual delivery time of 4-7 days has recently increased to 14 days, with some companies experiencing delivery times extended to seven times the original duration. Additionally, to keep up with Moore’s Law, the investment required for upgrading and developing equipment and technology in foundries continues to grow. Given the substantial investments in advanced production lines, foundries inevitably pass these costs onto customers in the form of increased tape-out fees. This has also led to rising costs in chip manufacturing.
03.How to Reduce Tape-Out Costs?
Under the influence of the aforementioned factors, the cost of chip tape-out has become a significant challenge for design companies. So, in the face of high tape-out prices, is there any way to reduce costs?
Wang Long, a senior director at Moore Elite, indicated that MPW (Multi Project Wafer) is a tape-out method that can help design companies reduce costs.
MPW refers to a wafer shared by multiple projects, where a single manufacturing process can accommodate multiple IC design tasks. It allows multiple integrated circuit designs using the same process to be placed on the same wafer for tape-out. After manufacturing, each design can obtain several chip samples, which is sufficient for experimental testing during the prototype design phase. In simple terms, several companies or institutions jointly purchase a set of masks, and the same wafer produced will contain several types of chips. After the wafer is cut, each party can take their respective chips home. The manufacturing costs are then shared among all participating MPW projects based on chip area, significantly reducing product development risks. According to Wang Long, MPW has a specific process, usually organized by wafer foundries or third-party service agencies. The MPW time points for various processes within a year are pre-set, with more advanced processes typically having higher MPW frequencies. Wafer foundries will pre-allocate multiple areas on the wafer and quote prices, allowing companies to book one or more areas based on their needs. This approach does impose some pressure on participants regarding design and development timelines. However, the benefits of MPW are evident; using multi-project wafers can lower chip production costs, provide practical opportunities for designers, and promote the transformation of chip design results, significantly benefiting the training of IC design talent, the development of small and medium design companies, and the research and development of new products. In comparison, the advantage of sharing masks is cost savings, but it may require waiting for the foundry’s time points, necessitating more time. Companies that are not constrained by budget or are in a hurry can utilize a full mask (Full-Mask) for their designs during the mass production phase. When the machines start, the profits are substantial. However, in the current context of severe capacity shortages, foundries have different attitudes towards customer product demands, competitive advantages, market prospects, and plans. They comprehensively consider order volumes, stability of future orders, and market prospects when making judgments. In reality, for most small and medium enterprises, in addition to price, they also face numerous challenges in the tape-out or mass production phases, including capacity and delivery times:
1. Lack of understanding of the foundry system, experience in process selection, and communication with foundries;
2. High entry barriers for mainstream foundries, making it difficult for emerging players to apply for expected processes or support, leading to high communication costs;
3. Lack of systematic supply chain management capabilities, especially during the ramp-up phase of mass production, leading to overly optimistic expectations regarding capacity, delivery times, and quality;
4. In a context of capacity shortages, the absence of a stocking mechanism can lead to panic ordering or ordering after receiving orders, resulting in capacity not keeping up with market demand. Additionally, fluctuations in delivery times and capacity can significantly increase communication costs and reduce efficiency for startups dealing with wafer foundries.
In response, small and medium chip design companies can seek collaboration with third-party operational service agencies that have resources, strength, and experience to jointly address supply chain challenges.Choosing a reliable third-party agency can assist design companies in overcoming current supply chain difficulties from technical, business, and capacity perspectives, providing optimal solutions.
In summary, companies in these demand sectors can benefit from the services provided by tape-out service providers.
04.ConclusionThe chip development project requires a lengthy process from product definition, design, verification, and simulation to the final tape-out. As the “ultimate test,” any small oversight during the preceding lengthy process can lead to tape-out failure, which often means the company faces losses starting from tens of millions of dollars and a missed market opportunity of at least six months. For many companies, tape-out failure is an unbearable pain. Therefore, chip design companies, manufacturers, and related industry service platforms and institutions should work closely together, complementing each other’s strengths to jointly solve the “tape-out dilemma” that developers face.
Recommended Resources
