When using I2C, have you encountered the following issues:
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An I2C bus that communicates without issues, but adding a few slave devices causes communication problems.
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An I2C bus that communicates without issues, but adding a level shifting circuit results in poor communication.
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An I2C bus that communicates without issues, but adding an ESD protection TVS diode leads to communication problems.
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An I2C bus that communicates without issues, but adding a 500-ohm resistor for ESD protection causes communication issues.
This article will break down the following points:
1. I2C bus hardware.
2. I2C bus communication speed.
3. Selection of pull-up resistor power supply voltage on the I2C bus.
4. Calculation of the pull-up resistor value range on the I2C bus.
5. Comparison of the maximum and minimum values of pull-up resistors on the I2C bus.
1. I2C Bus Hardware
As shown in the figure below, this is a typical application case provided by the I2C standard documentation.
From the above figure, we can see that I2C hardware has the following characteristics:
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Simple hardware connections, where different devices can communicate using just two wires.
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Pull-up resistors are added to each communication line.
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The pull-up power supply voltage has multiple names, meaning that these voltages can take different values.
These characteristics are also advantages of I2C communication compared to other communication interfaces.
2. I2C Bus Communication Speed
I2C supports multiple communication speeds; for example, the following chip supports three speed modes. Additionally, it can be noted that the 1Mbit/s mode requires a driving current of 20mA. Pay attention to this point, as it will be discussed later.
Next, let’s look at an MCU from NXP, the inventor of I2C, the i.MX RT1170:
This MCU supports five communication speed modes.
3. Selection of Pull-Up Resistor Power Supply Voltage on the I2C Bus:
As shown in the figure below, chip A and chip B communicate via I2C; the voltage selection for VCCX must meet the following two rules:
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The low voltage chip must output a high level that can be recognized by the high voltage chip, meaning VOH must be greater than VIH, where VIH is calculated as 0.7*VCC.
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If the pull-up resistor voltage VCCX is greater than the low voltage powered chip, it must be ensured that this voltage does not damage the IO.
According to the above rules, there are six different power supply voltage combinations as follows:
From the information in the above table, it can be seen that if the IO voltage tolerance of the low voltage powered chip is sufficiently high, communication can occur normally by selecting the pull-up voltage to match the high voltage chip side.
If the IO does not have high voltage tolerance characteristics, then all the above combinations are not feasible, and a level shifting circuit must be added.
4. Calculation of Pull-Up Resistor Value Range on the I2C Bus:
Now let’s look at how to design the resistor value range that this article focuses on.
Calculation of the minimum value of Rp:
First, let’s see what the minimum value of Rp is related to. As shown in the figure below, this is the case when the SDA level is pulled low; at this time, the output level is VOL. The smaller the value of Rp, the greater the voltage will be due to the voltage division between this resistor and the conduction resistance of Q2. In the extreme case, it is 0 ohms, at which point SDA will always be pulled high to VCC.
According to the standard data, the following table shows thatVOL cannot exceed 0.4V(VDD>2V).
If powered at 1.8V, then VOL cannot exceed 0.2*1.8=0.36V.
Using the formula, calculate the value of Rp(min).
Based on different power supply voltages and driving currents, the results are shown in the following table:
Calculation of the maximum value of Rp:
First, let’s look at the process of the SDA and SCL signals transitioning from low to high, as shown in the figure below:
Chip B input remains at 0, and Q2 NMOS is off. Chip A input switches from 1 to 0, pulling the SDA signal low through Q1 NMOS, and the SDA signal voltage rises from low to high. Due to the presence of capacitance Cb (Cb is the bus capacitance, including the capacitance of the chip pins and the capacitance of the traces), this process will take some time, and different communication speeds have different time requirements. The larger the values of Rp and Cb, the longer the voltage rise time.
The figure below shows the standard requirements for rise time at different communication speeds.
How to calculate the maximum value of Rp?
We can assume a worst-case scenario where the bus capacitance Cb is taken at its maximum value.
Now let’s calculate the maximum value of Rp:
The waveform rise time is RC charging, which follows an exponential rise curve, and the calculation formula is as follows:
From the above formula, we can obtain
Rise Time Tr=t2-t1=0.8473RC
Based on the above speed modes, the following table shows the resistance calculation data:
Organizing the above maximum and minimum values into a table yields the following:
Multiple highlighted areas indicate that the calculated minimum value of the pull-up resistor is greater than the maximum value, as shown graphically below:
From this data, it can also explain why ST’s chips are designed for a driving current of 20mA in Fast Mode Plus mode (1000kbps), rather than 8mA.
Only a 20mA driving current can ensure that the calculated maximum value of the pull-up resistor is greater than the minimum value.
At this point, some may wonder why their I2C design has always used a 4.7K pull-up resistor without any issues. Is there a problem with the above calculations?
This phenomenon can be easily explained; many products do not have a bus capacitance that reaches the maximum value given by the standard. For example, if there are fewer than five chips on the bus, we can recalculate with a bus capacitance of 50pF and obtain the following data:
It can be seen that when the bus capacitance is reduced to 50pF, the calculated maximum value of the pull-up resistor for all modes is greater than the minimum value.
Additionally, under conditions not exceeding 400Kbps, the maximum pull-up resistor can be set to 7K, so many products will not have issues even if the design pull-up resistor is 4.7K.
Furthermore, we can see that in high-speed mode (3.4Mbps), the range between the maximum and minimum resistor values is not large, which complicates actual circuit design. This issue also has solutions.
In high-speed mode, if the bus capacitance exceeds 100pF, a current source can replace the pull-up resistor to shorten the rise time. The original text provided by the standard is as follows:
There is also an Ultra Fast mode (5Mbps), which uses push-pull output for higher speeds and can only transmit in one direction. Interested readers can look up more information.
Summary:
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Under the parameters provided by the I2C standard, there are indeed abnormal situations where the calculated minimum value of the pull-up resistor exceeds the maximum value.
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In actual circuit design, the smaller the bus capacitance and the lower the communication speed, the greater the design margin for the pull-up resistor.
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The pull-up resistor scheme for open-drain communication is the main contradiction affecting the I2C bus speed, and higher speed communication modes use current sources instead of pull-up resistors or directly use push-pull output for communication.
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