Understanding Start, Data, and Stop Bits in Serial Communication

▶ Data Format

Before introducing the data sending and receiving process in asynchronous communication, it is necessary to clarify the data format in asynchronous communication.

Asynchronous communication specifies that the transmitted data format consists of a start bit, data bits, parity bit, and stop bit, as shown in the diagram (the parity bit is not depicted in this diagram since it is optional; if present, it should be after the data bits and before the stop bit).

Asynchronous Communication Data Format

(1) Start Bit:The start bit must be a logic 0 level lasting for one bit time, marking the beginning of the transmission of a character, allowing the receiver to synchronize its receiving clock with the sender’s data.

(2) Data Bits:The data bits immediately follow the start bit and are the actual valid information in the communication. The number of data bits can be agreed upon by both parties, usually 5, 7, or 8 bits; standard ASCII code is 0~127 (7 bits), and extended ASCII code is 0~255 (8 bits). During data transmission, the low bits of the character are sent first, followed by the high bits.

(3) Parity Bit:The parity bit only occupies one bit and is used for odd or even parity; it is not mandatory. If odd parity is used, the total number of logic high bits must be odd; if even parity is used, the total number of logic high bits must be even.

For example, if the transmitted data bits are 01001100, the odd parity bit would be 0 (to ensure an odd number of 1s), while the even parity bit would be 1 (to ensure an even number of 1s).

Thus, the parity bit is merely a simple logical high or low state for the data, without making substantial judgments about the data. This allows the receiving device to know the state of a bit and potentially determine if noise has interfered with communication and whether the transmitted data is synchronized.

(4) Stop Bit:The stop bit can be 1 bit, 1.5 bits, or 2 bits and can be set by software. It must be a logic 1 level, marking the end of the transmission of a character.

(5) Idle Bit:The idle bit refers to the period from the end of one character’s stop bit to the start of the next character’s start bit, indicating that the line is idle and must be filled with a high level.

▶ Data Sending Process

Once the data format for asynchronous communication is clear, data can be sent according to the specified format. The specific steps for sending data are as follows:

(1) After initialization or when there is no data to send, the sender outputs logic 1, which can have any number of idle bits.

(2) When data needs to be sent, the sender first outputs logic 0 as the start bit.

(3) The sender then begins to output the data bits, starting with the lowest bit D0, followed by D1, and finally the highest bit of the data.

(4) If there is a parity bit, the sender outputs the parity bit.

(5) Finally, the sender outputs the stop bit (logic 1).

(6) If there is no information to send, the sender outputs logic 1 (idle bit); if there is information to send, it proceeds to step (2).

▶ Data Receiving Process

In asynchronous communication, the receiver determines the time length of each bit based on the receiving clock and baud rate factor. Below is an example with a baud rate factor of 16 (the receiving clock shifts the input signal once every 16 clock cycles).

(1) Communication begins, and the signal line is idle (logic 1). When a transition from 1 to 0 is detected, the receiving clock starts counting.

(2) When the count reaches 8 clock cycles, the input signal is detected. If it is still low, it confirms that this is the start bit and not an interference signal.

(3) After detecting the start bit, the receiver checks the input signal every 16 receiving clock cycles and takes the corresponding value as the D0 bit data.

(4) After another 16 receiving clock cycles, the receiver checks the input signal again and takes the corresponding value as the D1 bit data, continuing until all data bits are input.

(5) Check the parity bit.

(6) After receiving the specified number of data bits and the parity bit, the communication interface circuit expects to receive the stop bit (logic 1). If the logic 1 is not received at this time, it indicates an error, and a “frame error” flag is set in the status register; if there is no error, all data bits are checked for parity, and if there is no parity error, the data bits are taken from the shift register to the data input register; if there is a parity error, a “parity error” flag is set in the status register.

(7) Once all information in the frame has been received, the high level on the line is treated as an idle bit.

(8) When the signal changes back to low, the next frame detection begins.

This is the entire process of data sending and receiving in asynchronous communication.

To better understand serial communication, we need to understand several basic concepts in serial communication.

(1) Sending Clock: When sending data, the data to be sent is first placed into the shift register, and then under the control of the sending clock, the parallel data is shifted out bit by bit.

(2) Receiving Clock: When receiving serial data, the rising edge of the receiving clock samples the received data, detects the data bits, and shifts them into the receiving shift register, ultimately forming the parallel data output.

(3) Baud Rate Factor: The baud rate factor refers to the number of clock pulses required to send or receive 1 data bit.