The Rise of RISC-V: SiFive Launches Five New RISC-V Cores

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SiFive Launches Five New RISC-V Cores, Accelerating the New Wave of AI Workloads

SiFive announced the release of its second-generation Intelligence™ series in September 2025, which includes five new or upgraded versions of AI acceleration IP cores:X160 Gen 2, X180 Gen 2, X280 Gen 2, X390 Gen 2 and XM Gen 2. These cores cover a wide range of applications from IoT and edge devices to high-end data center AI inference and training, integrating scalar, vector, and matrix computation capabilities to meet diverse AI application needs.

Core Highlights:

• New Product Line: X160 Gen 2 and X180 Gen 2 are newly designed additions; X280, X390, and XM are upgraded versions with re-tuned performance and energy efficiency.

• Wide Application Coverage: From edge devices to data centers, suitable for AI model deployment across various scales and power budgets.

• Integration of Three Computing Modes: Supports scalar, vector, and matrix operations, reflecting dual optimization for large-scale matrix computations (such as Transformers and neural networks) and small edge inference.

In the past, many AI accelerations relied on GPUs, TPUs, or dedicated tensor cores, while SiFive’s combination approach—balancing scalar/vector/matrix in a single IP core—promises a more flexible, energy-efficient, and easily deployable solution across multiple scenarios. This is a significant step for domestic chip design companies and AI model deployers to closely monitor and quickly follow up.

Original link:https://www.eenewseurope.com/en/sifive-launches-new-risc-v-ai-ip-with-scalar-vector-and-matrix-compute/

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Efinix Expands Titanium Series FPGAs, Targeting AI and Edge Computing Explosion

Efinix announced further upgrades to its Titanium series FPGA product line, introducing new devices using TSMC’s 16/12nm process, featuring up to 25.8 Gbps transceivers, 64-bit RISC-V SoCs, and enhanced MIPI data transfer rates. These updates enable Titanium FPGAs to better support real-time decision-making and video/sensor data processing in applications such as industrial automation, robotics, automotive systems, handheld medical devices, and edge platforms.

Company Overview

• Founded: 2012, founded by FPGA industry veterans Sammy Cheung and Tony Ngai. Both accumulated years of FPGA architecture and product experience at companies like Altera (now Intel FPGA) before joining Efinix.

• Headquarters and Distribution: Headquartered in Cupertino, California, USA, with branches in Malaysia, Hong Kong, Japan, Germany, and other locations.

• Employee Size and Market Performance: The company operates in multiple countries with approximately a hundred employees. By 2022, it had shipped over ten million FPGA devices.

Original link:https://embeddedcomputing.com/technology/processing/semiconductor-ip/efinix-expands-titanium-fpgas-featuring-258-gbps-transceivers-and-64-bit-risc-v-socs

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Paper Guide: Combating Hardware/Software Tampering with FPGA + TEE and RISC-V

In the paper “Trust is Good, Monitoring is Better,” researchers propose a runtime monitoring scheme that combines RISC-V SoCs with FPGA-based Trusted Execution Environments (TEEs), specifically targeting potential hardware backdoors and malicious firmware attacks in robotic systems.

Core Highlights

• Architecture Based on RISC-V: The SoC’s controller core uses a 32-bit RISC-V CPU, supporting SCI-bus interfaces and peripherals like force sensors, providing the foundation for control and perception in industrial robotic scenarios.

• Monitor in TEE + FPGA: The monitor implemented in FPGA is deployed within the TEE, achieving true isolation monitoring of hardware and software behaviors, thus preventing system attackers from tampering with or disabling monitoring functions.

• Monitoring Includes Timing Behavior at Hardware/Software Levels: Expected behaviors are defined through formal constraints and timing specification languages (MTSL); the FPGA hardware monitoring unit is sensitive to single-cycle violations; software uses statistical timing monitors (STMo) to compare execution time distribution characteristics to detect tampering.

• Supply Chain Security: The monitor is programmed into the TEE only after chip packaging, ensuring that backdoors or tampering are difficult to insert throughout the design, production, and packaging supply chain.

Original link:https://www.researchgate.net/publication/395253183_Trust_is_Good_Monitoring_is_Better_FPGA-_TEE-Based_Monitoring_for_Malware-Detection

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Open Source Collaboration: The Driving Force of Innovation—Supporting RISC-V Open Standards

In Meer’s article “Collaboration: the real engine of innovation,” the author emphasizes that technological change is never a solitary genius’s monologue but a trend driven by shared standards, open architectures, institutional support, and interaction among users/researchers/companies. The article points out that from early transistors and microprocessors to network protocols like TCP/IP, all have spread and innovated based on “modular architecture + open standards.”

The Role and Resonance of RISC-V

• Exemplar of Open Architecture: RISC-V, as an open-source instruction set architecture, is a real-world example of collaboration and standardization. It allows different vendors, academic institutions, and even individual designers to tailor and extend their processors or AI accelerators based on it, reducing redundant efforts and accelerating innovation.

• Ecological Sharing: Through open licensing and modular design, the development of RISC-V is not from a single company but a multi-party collaborative process involving startups, organizational alliances, and community users.

• Wide Applicability: From automotive electronics, AI inference/training to edge computing, RISC-V is seen as a customizable platform for hardware design, meeting diverse scenario needs.

Technological innovation is not just about “invention,” but also about how to “collaborate + standardize + iterate continuously.” RISC-V is the key soil for practicing this innovation paradigm. For domestic developers, chip companies, and industrial policymakers, this provides a clear direction—advocating open standards and ecological cooperation will lead to more sustainable and resilient innovation capabilities.

Original link:https://www.meer.com/en/97419-collaboration-the-real-engine-of-innovation

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Small Products, Big Inspiration: Exploring RISC-V Product Possibilities through the MK10 Macro Keyboard

Recently, Waveshare launched the MK10 macro keyboard model, which provides a great reference sample, especially for teams/entrepreneurs looking to create small and refined products using RISC-V. Its specifications and design offer many valuable insights. Here’s a summary and thoughts on potential paths for RISC-V:

Key Points Overview (Design Features of MK10)

• MK10 is a macro keyboard similar to a “Stream Deck,” featuring 10 mechanical keys, with keycaps that are 0.85-inch LCD displays capable of showing images/videos + layer overlay effects.

• In addition to the main keys, there is a 2.01-inch auxiliary display for showing status, custom information, etc.

• Dual system architecture: the main controller uses Allwinner T113-S3 (dual-core ARM Cortex-A7 + HiFi4 DSP) running Linux; the sub-controller is a GD32 MCU running QMK firmware, ensuring low-latency mechanical key responses.

• Careful design of the shell and physical structure: aluminum alloy top cover, high transparency hardened acrylic lens, high key lifespan (50 million presses), can be placed flat or at a 40° angle.

Original link:https://www.cnx-software.com/2025/09/09/qmk-compatible-macro-keyboard-features-0-85-inch-lcd-keycaps-2-01-inch-display/

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