This article is compiled by Semiconductor Industry Review (ID: ICVIEW) from semiwiki.
The rise of RISC-V in the DPU field creates a rare opportunity to reshape the competitive landscape of the industry.
Data centers are often seen as a battleground between CPUs and GPUs. However, behind this highly publicized competition, another quiet revolution is taking place: ARM is quietly replacing Intel and AMD in the data processing unit (DPU) market.
DPUs (also known as SmartNICs) are responsible for the “pipeline” of data centers. They alleviate network load by managing packet processing, TCP/IP, and RDMA. They handle storage services such as compression, encryption, and NVMe-over-Fabrics (NVMe-oF). They enforce security isolation, which is crucial in multi-tenant cloud environments where trust boundaries are constantly tested. Additionally, they are responsible for executing orchestration tasks that would otherwise waste valuable CPU cycles.
NVIDIA, Marvell, AMD, and Broadcom all use ARM cores in their DPUs. The reason is simple: ARM cores are small, low-power, and licensable, and they have already been embedded into network chips. By the time Intel launched its Infrastructure Processing Unit (IPU) initiative, ARM had already captured the entire ecosystem and set the standards.
Why Now?
The global data processing unit (DPU) market is expected to grow from $1.5 billion in 2023 to approximately $9.8 billion by 2032, with a compound annual growth rate (CAGR) of up to 22.8%. Dataintelo attributes this growth to the rapid increase in data generation and the demand for efficient data management and processing solutions across various industries. Currently, ARM cores dominate DPU shipments, while Intel continues to promote its IPU but has yet to gain widespread market traction.
Meanwhile, RISC-V is gaining momentum in adjacent fields. Companies like Fadu from Seoul have integrated RISC-V cores into their enterprise SSD controllers for I/O scheduling and latency optimization, and SiFive is using RISC-V to accelerate I/O. Orchestration and security processors also frequently rely on lightweight RISC-V designs, such as OpenTitan. These roles are naturally related to that of DPUs. At the same time, geopolitical factors favor diversification: particularly, China is accelerating its adoption of RISC-V, and DPUs are critical infrastructure components where sovereignty is paramount.
Market expansion, ARM’s lock-in, and the desire for architectural alternatives among hyperscalers lay the groundwork for RISC-V to enter the DPU space.
Opportunities for RISC-V in DPUs
Unlike ARM, RISC-V offers an open ISA that companies can customize according to their specific workloads. This is particularly important for DPUs that integrate various functional modules. Network engines for packet flows, storage accelerators for compression and NVMe-oF, security modules for isolation, and control plane CPUs for orchestration. RISC-V allows vendors to use custom instructions to fit these roles without relying on ARM’s fixed roadmap.
Today’s DPUs typically use ARM Cortex-A core clusters (ranging from Cortex-A53 to A72) to handle control plane and lightweight computing functions. Some RISC-V vendors (such as Akeana) support simultaneous multithreading (SMT) with up to four threads per core (Electronics360, 2024), thereby improving throughput and utilization for high memory or I/O latency workloads (such as networking and packet processing). The latest RISC-V vector extensions can naturally map to packet processing, encryption, and storage acceleration.
The emerging matrix extensions will extend programmability into AI inference and security domains. The architecture from startup Simplex Micro integrates scalar, vector, and matrix execution within a time-scheduling framework, leveraging RISC-V’s scalability to deliver deterministic performance across various AI and HPC workloads. Finally, RISC-V avoids ARM’s royalty fees while maintaining compatibility with open-source stacks like Linux, TensorFlow, and PyTorch.
Understanding RISC-V’s Scalar to Matrix Roadmap
This moment is noteworthy not only because of the promotion of another IP vendor but also due to the way RISC-V itself is evolving.
The ISA was initially dedicated to scalar computing—providing small, efficient cores for microcontrollers, embedded systems, and simple processors supporting Linux. Over the past few years, RISC-V has steadily added vector extensions, achieving data-parallel acceleration that naturally maps to networking, storage, and encryption workloads. Recently, its roadmap has expanded to include matrix extensions aimed at incorporating AI inference and other matrix-math-intensive tasks into the same ISA framework.
This evolution from scalar to vector to matrix reflects the performance requirements of DPUs. DPUs must handle scalar control plane logic, vectorizable packet and encryption streams, and increasingly matrix-oriented telemetry and security inference tasks. In other words, the RISC-V roadmap provides a complete set of elements for truly programmable DPUs.
Currently, multiple companies are working to realize this vision.
Akeana, with its SMT-supporting design and AI matrix computing engine, is one of the first companies to apply RISC-V directly to data center-level computing.Ventana Micro Systems is building server-grade RISC-V processors with a clear path from scalar to vector workloads to meet the demands of hyperscale computing. In Europe, SemiDynamics focuses on configurable vector cores tailored for data-intensive and AI-centric applications.
SiFive is emphasizing RISC-V cores that support Linux and vector operations, aimed at meeting the needs of HPC and infrastructure. Andes Technology has expanded its cores to include vector and DSP capabilities for embedded acceleration. Simplex Micro is developing a unified scalar/vector/matrix architecture with programmable extension capabilities, aimed at covering infrastructure solutions from edge to data center level. At the research level, China’s “Xiangshan” has conducted experiments on scalar and vector unification under the same architecture.
Leapfrogging or Strengthening ARM?
The question is not only whether RISC-V can replace ARM but also whether it can expand the definition of DPUs themselves. ARM’s current dominance in the DPU space relies on scalar cores plus fixed accelerators. RISC-V offers a leapfrogging path by integrating scalar, vector, and matrix programmability into a single platform. This does not necessarily come at the expense of ARM—in fact, ARM could even adopt RISC-V’s vector and matrix extensions to solidify its own DPU position.
For the broader industry, RISC-V’s rise in the DPU space presents a rare opportunity to reshape the competitive landscape. Companies are no longer constrained by ARM’s licensing model but can adjust architectures according to their needs. This is particularly important for hyperscale computing companies looking to optimize power consumption, performance, and autonomy. RISC-V also avoids monopolistic situations: rather than having a single vendor dominate the roadmap, an open ecosystem can be established to foster multiple development paths.
With RISC-V, companies like Qualcomm or any major vendor will dominate—able to design unique custom CPUs optimized for their DPU architectures without relying on ARM’s licensing terms and roadmap. As DPUs become central to data center infrastructure, this independence could become a key differentiator.
The time has come. AI-driven data center architectures are thriving, and DPUs are no longer just for networking but are used to coordinate computing, storage, and AI processes. In this world, DPUs that combine scalar, vector, and matrix programmability appear more attractive than those that merely integrate scalar ARM cores and fixed-function engines.
Just as ARM discovered and capitalized on the DPU opportunity beyond Intel and AMD, RISC-V now offers the chance to redefine this category. Vendors do not need to confront NVIDIA directly in the GPU space or attempt to revive the CPU but can achieve leapfrogging development through a programmable DPU platform that can reshape data center infrastructure. This will be a comeback story—not a repetition of old battles but the opening of new fronts.
Whether it can replace ARM or x86, the industry often describes RISC-V as a story in the CPU space. However, the more disruptive opportunity may lie in the control plane of data centers. ARM created a DPU franchise that Intel and AMD never anticipated, and now RISC-V has the opportunity to redefine this category with vector and matrix programmability.
Ultimately, ARM and RISC-V may coexist in the DPU space: ARM maintains its dominance while RISC-V offers an open, customizable alternative. As the market matures, this will provide more architectural choices for vendors and hyperscale computing providers.
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