SiFive is a global leader in RISC-V chip design, founded in 2015 by the inventors of the RISC-V architecture, and headquartered in California, USA. As a core driver of the RISC-V ecosystem, SiFive provides processor IP, toolchains, and customized chip solutions based on the RISC-V instruction set, covering a wide range of application scenarios from edge computing to data centers.
During quarterly performance communications, Nvidia CEO Jensen Huang is always asked a core question—will the increasing number of custom ASIC chips erode its dominance in the AI field? In response to such inquiries, Huang consistently downplays the competitive pressure from custom ASICs and emphasizes the irreplaceable high programmability advantages of GPUs in a dynamically changing technological environment.
However, market trends have not stalled due to Huang’s views. Key player in chip design, SiFive, continues to push forward with core design R&D based on the RISC-V architecture, with products covering a wide range from IoT terminal devices to high-end AI accelerators. Google’s Tensor Processing Unit (TPU) and Tenstorrent’s Blackhole accelerator both utilize SiFive’s related technology solutions.
SiFive has publicly disclosed an important development: its core designs based on the RISC-V architecture have provided chip support for five of the “seven giants” in the tech industry. These “seven giants” include Alphabet, Amazon, Apple, Meta, Microsoft, Nvidia, and Tesla. Although some collaborations among these companies may not be directly related to AI business, the frequent inquiries from analysts to Huang regarding custom ASIC chips indicate a growing market interest in the custom chip sector.
Many may be aware of SiFive’s RISC-V development boards created for Meta and Microsoft, but in reality, the company’s core business is not hardware manufacturing but the design and licensing of chip core IP—this business model is very similar to that of the UK chip design leader Arm Holdings. Next, we will focus on SiFive’s core business and delve into the technical characteristics and market value of its intellectual property (IP) products.
At the recent AI Infra Summit, SiFive, as a leading company in RISC-V chip design, officially launched its second-generation intelligent core series products. The newly released products not only include new designs for edge AI application scenarios such as robotic sensing but also comprehensively upgrade its X200 series, X300 series processors, and XM series accelerators, further enhancing its product matrix.
It is important to note that all of the aforementioned core designs are based on an eight-stage dual-issue in-order superscalar processor architecture. In terms of application scenarios, they are not designed for general-purpose CPUs (such as the CPUs responsible for basic computations in our daily computers and smartphones) but focus on high-performance computing needs in specific fields.
Specifically, SiFive’s Intelligence series cores are positioned as “Accelerator Control Units (ACUs),” with the core function of ensuring that the tensor cores and matrix multiplication accumulation units (MACs) in customer chips can continuously and stably access data, avoiding efficiency drops due to insufficient data supply, thereby maximizing the performance potential of AI accelerators.
SiFive’s product logic is very clear: customers do not need to invest significant resources in independently developing customized control units; they can directly adopt the mature solutions of SiFive’s Intelligence series through licensing cooperation. This model has been recognized by the market, with Google, Tenstorrent, and several tech giants choosing to advance their chip projects in this way.
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In the newly released SiFive second-generation intelligent cores, the X160 and X180 products are primarily aimed at low-power application fields, such as IoT terminal devices, drone control systems, and robotic perception modules. The two cores have clear architectural distinctions: the X180 is based on a 64-bit architecture design, while the X160 adopts a 32-bit RV32I instruction set architecture, allowing for flexible adaptation to the computing power and power consumption needs of different devices.
In terms of deployment flexibility, customers can cluster the X160 and X180 cores into groups containing up to four cores, and multiple such quad-core clusters can be integrated into a single chip to meet varying computational demands. In terms of hardware specifications, both cores support 128-bit wide vector registers and are equipped with 64-bit wide data transmission paths.
The advantage of this hardware configuration is its ability to efficiently process various modern data types, including the INT8 data type commonly used in edge computing and the BF16 data type widely used in AI computations. For devices equipped with AI accelerators specifically optimized for these data precisions, the data processing capabilities of the X100 series cores can significantly enhance overall computational efficiency.
Notably, in the second-generation products, the communication mechanism between the X100 series cores and accelerators has undergone significant upgrades. In addition to retaining the “Vector Co-Processor Interface Extension (VCIX)” from the previous generation—which allows for high-bandwidth access to the CPU core’s vector registers, ensuring data transmission speed—SiFive has also introduced a new “Scalar Co-Processor Interface (SSCI)” for the second-generation cores. Through this new interface, accelerators can directly access the CPU’s registers and support custom RISC-V instructions, further reducing communication latency between hardware and enhancing collaborative computing efficiency.
In addition to the low-power X100 series cores, SiFive has also simultaneously launched the second-generation products of the X280 and X390 series processor cores, focusing on high-performance computing needs.
From an infrastructure perspective, the X280 Gen 2 and X390 Gen 2 continue the eight-stage dual-issue in-order execution pipeline design and support flexible cluster configurations—customers can configure them into single-core, dual-core, or quad-core clusters based on actual application needs. In terms of vector register width, both cores maintain the advantages of the previous generation: the X280 Gen 2 supports 512-bit wide vector registers, while the X390 Gen 2 supports 1024-bit wide vector registers, providing a hardware foundation for large-scale data parallel computing.
Looking back at historical collaboration cases, as early as 2022, Google had adopted SiFive’s X280 core to manage the matrix multiplication units (MXUs) in its Tensor Processing Units (TPUs), demonstrating the maturity of this core series in the high-performance accelerator control field.
Compared to the previous generation products, the upgrades of the second-generation X200 and X300 series cores focus on three aspects:
Instruction Set Update: A comprehensive upgrade to the RVA23 instruction set architecture, adding hardware-level support for the BF16 data type, and for the first time introducing support for the MXFP8 and MXFP4 micro-scaling data types under the OCP standard. Among these, the MXFP8 and MXFP4 data types have recently garnered industry attention because OpenAI chose to use these micro-scaling data types when releasing its open-weight model gpt-oss to balance computational precision and hardware costs.
Cache Architecture Optimization: The X280 Gen 2 has restructured its cache hierarchy. The previous generation adopted a three-level cache architecture of “L1+L2 + shared L3,” while the second-generation product simplifies this to a more flexible customized architecture, eliminating the L3 cache and increasing the shared L2 cache capacity of each core cluster to a maximum of 1MB. SiFive states that this adjustment not only improves the utilization of cache resources but also reduces chip area occupation, lowering hardware costs.
Significant Performance Improvement: According to data released by SiFive, the higher-end X390 Gen 2 core achieves four times the computing power of the first-generation X280 core, with data throughput increased by 32 times. In a quad-core cluster configuration, the X390 Gen 2 can achieve a data movement speed of 1TB per second, providing strong support for large-scale data processing.
In terms of product positioning, SiFive defines the X390 Gen 2 as both an “independent AI accelerator core” and a “high-performance ACU.” As an independent AI accelerator core, its large-capacity vector registers can directly undertake some AI computation tasks; as an ACU, the SSCI interface validated in the previous generation can further optimize its collaborative efficiency with accelerators, fully leveraging hardware performance.
In addition to the upgrades of the CPU cores, SiFive has also iterated its XM series ready-to-use AI accelerator IP to ensure compatibility with the latest X390 Gen 2 cores. The XM series products first debuted last summer, and their core value lies in providing customers with a standardized design blueprint for “scalable AI accelerators,” helping customers quickly build AI computing hardware that meets their needs.
The second-generation XM cluster has achieved significant breakthroughs in hardware configuration: deeply integrating the internal matrix math engine with four upgraded X390 Gen 2 cores. According to SiFive’s test data, at a working frequency of 2GHz, a single XM cluster can provide 64 teraFLOPS of FP8 computing performance. More importantly, this cluster supports multi-node expansion, allowing for the construction of chips with AI computing performance exceeding 4 petaFLOPS through multi-cluster collaboration, meeting different needs from edge AI to data center-level AI computing.
Currently, all CPU cores and accelerator IP released by SiFive are open for licensing, allowing customers to initiate customized chip development projects based on their business needs. According to SiFive’s plan, the first customer-customized chip based on the second-generation intelligent cores and XM accelerator IP is expected to enter mass production and market in the second quarter of 2026. This timeline also signifies that the commercialization of RISC-V architecture in the high-end AI chip field will see a critical breakthrough in the next two years.
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