The Battle of the Three Technologies: The Intersection of CPO, PCB, and HBM Technologies and Their Industrial Implementation

Key Insight: What you see is the “dividend growth curve” behind three technologies, but the system sees three completely different technical matrices: Co-Packaged Optics (CPO) in the structural revolution of “optical-electrical co-packaging”, Printed Circuit Board (PCB) in the underlying support of “substrate materials and interconnections”, and High Bandwidth Memory (HBM) in the cutting-edge breakthrough of “stacked memory + bandwidth breakthrough”.

1. Why are these three technologies simultaneously pushed to the forefront?

In the era of AI, data centers, and computing power infrastructure explosion, hardware bottlenecks extend from the chip itself to three major links: “interconnection”, “memory”, and “packaging/substrate”:

• The computing core is becoming increasingly powerful, but the high-speed channels that need to be opened are becoming narrower, entering the “interconnection bottleneck” stage.
• Memory bandwidth, power consumption, and packaging density have become performance limits.
• Materials, substrates, heat dissipation, and signal integrity have become critical winning points beyond just “who can run faster”.

Therefore:

• CPO represents the structural revolution of the “next step in optical-electrical interconnection”.
• PCB faces the transformation from ordinary circuit carriers to “high frequency, high layer count, high density” substrates.
• HBM is born to address the bandwidth bottleneck of traditional DDR/GDDR memory, representing a “memory structure leap”.

Although the three seem different, they form a “computing power ecosystem”: substrate → packaging/interconnection → high-speed memory. Whoever seizes the key link in this chain will grasp the next opportunity in future hardware.

2. Technical Breakdown: The Essential Logic and Dynamics of CPO, PCB, and HBM

2.1 CPO: Optical-Electrical Co-Packaging, Reshaping Interconnection Structure

Definition and Evolution CPO refers to placing optical modules (including lasers, modulators, photodetectors) and electronic processors (such as switch chips, ASICs) in the same package or very close packaging, thereby shortening the electro-optical/electro-optical conversion path, greatly improving signal integrity, power consumption, and bandwidth density. Why It Matters

• In traditional data centers/network devices, electrical signals are transmitted over long distances through PCBs to front panel optical modules, where losses, power consumption, and heat become bottlenecks. CPO reduces this path to a few millimeters or even smaller.
• With the scaling of AI training/large models, bandwidth demand, interconnection density, and power density are all exploding. CPO is seen as the key to breaking through the “electrical interconnection barrier”. Key Challenges
• Heat dissipation and thermal management: High-sealing, high-power packaging with stacked optical-electrical modules has extremely high heat dissipation requirements.
• Manufacturing/packaging complexity: Photonic-electronic, 2.5D/3D packaging, silicon photonic-electronic integration, high process difficulty.
• Ecology and standards are still being improved: CPO is still in the transition phase from “demonstration to mass production”. One-Sentence Evaluation: CPO is the “reconstructor of interconnection structure in the computing power era”; whoever achieves mass production and adapts to the ecosystem first will occupy the interconnection high ground of future computing power platforms.

2.2 PCB: From Circuit Carrier to High-Layer Substrate, Upgrading the Invisible Value Chain

Positioning and Evolution PCB (Printed Circuit Board) was once regarded as an “old chain, invisible” basic component. However, with the increase in chip speed, memory density, and packaging complexity, the technical threshold of PCBs is rapidly rising. Especially for AI servers, data center motherboards, and interconnection boards, the requirements for line density, layer count, and high-speed signal integrity are unprecedented. Upgrade Dimensions

• Increase in the number of layers: such as high-density substrates with more than 18 layers, even 100+ layers.
• High-speed signal/low-loss materials: migrating from traditional FR-4 to Rogers, metal core (MCPCB), low-Dk/low-Df materials.
• Thermal design and structural integrity: AI server boards require stability in high-temperature environments, and PCBs need to integrate heat dissipation, heat sinks, and metal substrate technologies. Why It Is Underestimated PCB may seem traditional, but in high-end hardware, it is both a “connector” and a “heat dissipation channel”, playing a key role in interconnection, packaging, and signal integrity. One-Sentence Evaluation: PCB is the “invisible foundation of computing power hardware”; although it may not be eye-catching in cutting-edge technology, it is a necessary foundation that must be built first.

2.3 HBM: The Breakthrough in Memory Bandwidth, Determining the Performance Ceiling of Computing Power Platforms

Definition and Evolution High Bandwidth Memory (HBM) is a type of memory structure that stacks DRAM chips (using TSV/micro-bumps) and places them in close interconnection with processors (such as silicon interposer/interconnection layer), achieving extremely wide data channels, high bandwidth, and low power consumption. Version evolution: HBM1 → HBM2 → HBM2E → HBM3 → HBM3E → HBM4, with bandwidth ranging from hundreds of GB/s to over TB/s. Why It Is Praised

• In GPU/XPU/AI accelerators, memory bandwidth has become a bottleneck, and HBM can provide several times the bandwidth of traditional DDR/GDDR.
• It has advantages in packaging density/power consumption control: shorter connections and lower power consumption. Challenges and Constraints
• Extremely high costs, strict yield requirements, and complex manufacturing.
• Thermal management difficulties: vertical stacking structures have complex heat dissipation. One-Sentence Evaluation: HBM is a “key link in the memory architecture moving towards computing power platforms”; its bandwidth, density, and power consumption performance directly determine the performance ceiling of future accelerators.

3. How Do These Three Technologies Intersect and Resonate in the Actual Industry Chain?

We see a clear industrial logic chain:

1. AI training/large models require extreme computing power + massive data processing + high bandwidth interconnection.
2. Interconnection is migrating from traditional cables/substrates to optical interconnection (CPO), with dual improvements in bandwidth density and power consumption.
3. Board-level structures (PCB) must shift from supporting traditional circuits to supporting high-frequency, high-speed, multi-layer, low-loss substrates.
4. The memory subsystem (HBM) becomes the bottleneck breakthrough point in the computing power platform, determining performance potential.

Specifically manifested as:

• In an AI training server, a large amount of HBM is needed next to the processor to support high-speed data pathways;
• These processors, memory, and interconnection modules are interconnected through PCBs or substrates, requiring high layer counts, high density, and high signal integrity;
• If ultra-high-speed interconnection to other processors or GPU clusters is also needed, CPO technology may replace traditional board-level interconnections, further enhancing bandwidth/reducing power consumption.

Therefore, these three technologies are not isolated but are three key nodes in the “hardware upgrade chain of computing power platforms”. Whoever holds an advantage in this chain may win in the future hardware race.

4. Future Scenario Simulation: Three Possible Paths

Optimistic Path

• CPO becomes the mainstream interconnection solution for data centers/AI servers, with significant advantages in bandwidth density and power consumption.
• PCB materials and high-layer substrates become widespread, leading to an explosion for high-end PCB manufacturers.
• HBM4 is produced, with bandwidth reaching several TB/s, and the computing power platform enters a new dimension. Result: Overall structural upgrade of hardware infrastructure, benefiting segmented manufacturers and material supply chains.

Baseline Path

• CPO is gradually promoted but does not completely replace traditional modules; high-end PCB growth remains steady, and HBM bandwidth continues to improve but costs remain high. Result: Growth is expected, but technological implementation and cost reduction remain key rhythms.

Pessimistic Path

• High costs and high technical thresholds lead to slow promotion of CPO; the PCB industry falls into homogenization, and HBM costs do not decrease, limiting adoption. Result: Delayed realization of technological dividends, lower-than-expected returns in the industry chain, and a decline in market enthusiasm.

5. Investment/Industry Perspective

1. Identify Vendor Roles: Which vendors are CPO solution providers? Which are high-end PCB manufacturers? Which are key vendors for HBM stacking/packaging? Distinguishing roles is crucial.
2. Understand Barriers and Costs: High technical thresholds but also high investments; who truly has mass production capabilities? Who can continue to reduce costs?
3. Focus on Cost Curves and Mass Production Nodes: For example, will CPO enter mass production in 2026-27? Will PCB material costs decrease? Will HBM4 be mass-produced?
4. Think in a Linked Manner, Do Not View in Isolation: Focusing solely on one technology may miss opportunities in the chain of “who breaks through first”.
5. Be Aware of Cycles and Valuation Expectations: Hardware infrastructure and computing power expansion is a major trend, but cost and cycle risks cannot be ignored.

6. Conclusion

CPO, PCB, and HBM may seem like three different technology stacks, but in the AI era, their true value lies in: building the foundation for the next computing power infrastructure.

• CPO is the “new chapter of optical interconnection”;
• PCB is the “underlying innovation of substrate materials”;
• HBM is the “performance threshold of memory bandwidth”.

In the next decade, it is not just about who makes chips, but also about who connects “substrate → packaging → memory” together, turning dividends into structural capabilities. The halo of technology is attractive, but what truly remains is a rigid commercialization chain, sustainable mass production capabilities, and indispensable segmented roles in the industry chain.

When the windfall dissipates, what remains is not who rises the fastest, but who has the deepest architecture and the strongest chain. When betting on the “three technologies”, do not just look at the heat, but also at the structure.