Author: Ariel D’Alessandro, Collabora
Abstract: With the rise of RISC-V, the demand for stable and scalable hardware testing infrastructure is becoming increasingly important. To fill this gap in the ecosystem, the RISE project and Collabora have integrated two RISC-V development boards (Banana Pi BPI-F3 and SiFive HiFive P550) into Collabora’s public LAVA testing lab. Utilizing tools like LAVA and Boardswarm, the project has achieved full remote automation from high-level operating system testing to low-level bootloader recovery and flashing. This provides the open-source community with a critical, publicly accessible RISC-V hardware in the loop testing platform, complete with documentation for developers to replicate.
The RISE (RISC-V Software Ecosystem) project, under the Linux Foundation, aims to accelerate the development of open-source software for the RISC-V architecture. A major challenge in the ecosystem is the lack of user-friendly and reliable RISC-V hardware in the loop testing platforms. Addressing this issue is crucial for fostering innovation and promoting the widespread adoption of RISC-V.
Collabora places great importance on hardware in the loop (HIL) testing for open-source software. We operate a large LAVA testing lab with nearly 400 devices covering about 70 models. This lab is used as a HIL testing platform by several open-source projects, including KernelCI, Mesa, and Apertis.
As part of the RISE RP012 project, we collaborated with RISE to bring RISC-V development boards into the Collabora LAVA lab. We have documented the entire solution to facilitate teams interested in building their own development board clusters. The development boards used are:
- Banana Pi BPI-F3
- SiFive HiFive Premier P550
The lab environment setup consists of two parts: LAVA support and low-level testing of the boot chain. The first part involves standard LAVA support, focusing on automatic power control, serial console control, and bootloaders that support network booting. Both devices can boot, control the u-boot bootloader, network boot the testing system, and drive tests via the serial port through LAVA. This is sufficient to support kernel and Linux user space testing.
The second part focuses on interactively testing the initial boot chain (u-boot, opensbi, etc.) at a low level. We utilized the Boardswarm board management service. For more information, please refer to our previous blog post[1], which introduces the features and uses of Boardswarm.
Understanding this process requires knowledge of the SoC boot process. After power-up, the first code executed is the hardwired BootROM code within the chip. This code is primarily responsible for loading and executing the first-stage bootloader (FSBL). During normal boot, this program is typically stored on local storage devices (SPI flash, eMMC, SD card, UFS, etc.). However, modern SoCs support download mode, allowing the first-stage bootloader to be uploaded via USB, commonly used for device initialization or recovery. Different manufacturers have different names for this mode, commonly referred to as “download mode.”
Almost all development boards have a way to enter this mode, such as pressing a button or adjusting DIP switches during power-up. The Banana Pi F3 uses a button press, requiring a slight hardware hack to simulate the press automatically. The SiFive board has a physical DIP switch and a small microcontroller that can configure the boot mode via the serial port. We added support for this serial interface in Boardswarm to enable power control and boot mode configuration.
Once the device enters download mode, the next step is to upload the bootloader. The protocol is defined by the SoC manufacturer. The Banana Pi simulates a USB storage device, expecting the FSBL to be written as a single file—we enabled this functionality in Boardswarm. The SiFive’s BootROM supports the Android fastboot protocol. Although Boardswarm already has fastboot “flash” command support, we extended the “stage” command for BootROM stage loading, indicating that data is only downloaded to memory and not written to storage.
After the FSBL upload is complete, the development board runs the software we specified. Both boards’ FSBLs are configured to boot via USB fastboot, facilitating the re-flashing of the bootloader on local storage. For the SiFive board, we added support for writing to SPI flash via fastboot for u-boot, avoiding vendor-specific commands and maintaining standard fastboot compatibility.
Overall, the entire process enables remote reset of the device, switching to download mode, and software replacement. Although the process is complex, the actual operation is relatively straightforward for both boards. The following illustration can further clarify:
After completing the above work, these two development boards have been integrated into the Collabora LAVA lab for upstream testing by projects like KernelCI. Friends interested in building their own lab can refer to the complete documentation.
- Banana Pi BPI-F3[2]
- SiFive HiFive Premier P550[3]
The documentation details the boot and support content for both platforms:
- Hardware preparation and BOM list
- u-boot boot chain source code and artifacts
- Bootloader update mechanism
- Boardswarm automation and remote control configuration
- Debian and Linux kernel testing artifacts
These integrations are an important milestone for RISC-V continuous integration and testing, laying a solid foundation for robust development of critical components like the Linux kernel and long-term platform stability.
References[1]
Blog post: http://news-and-blog/news-and-events/meet-boardswarm-a-new-open-source-tool-for-board-management-and-distributed-development.html
[2]
Banana Pi BPI-F3: https://lava.pages.collabora.com/docs/boards/spacemit-k1-bananapi-f3/
[3]
SiFive HiFive Premier P550: https://lava.pages.collabora.com/docs/boards/eic7700-hifive-premier-p550/
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