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In today’s article, I will share with you the “Four Essential Tools” of ASIC design: Fold, Expand, Retiming, and Resource Sharing.
Fold & Expand
Fold & Expand
One clock cycle produces a result using two multipliers, large area, fast speed.
Two clock cycles produce a result using one multiplier, small area, slow speed.
This process is called Folding, while Expanding can be seen as the reverse operation of Folding. In practical engineering, we use these two techniques appropriately according to our needs to achieve design optimization.
Improving speed and reducing area are two conflicting goals, so in specific designs, a trade-off is necessary. A good design aims to minimize idle time for logic that occupies a large area, achieving high reuse.
Retiming
It is often asked in written exams, what is Retiming technology?
Retiming is the process of adjusting timing. For example, when encountering complex combinational logic in a circuit with excessive delay, the timing may not be satisfied. In this case, pipelining technology is employed to insert registers in the combinational logic for operations, trading area for speed.
We know that any digital circuit can be equivalently represented as combinational logic plus D flip-flops. The combinational logic path between two D flip-flops determines the system’s operating frequency and the chip’s performance. Therefore, to improve the chip’s operating frequency, we use pipelining technology to insert registers into the combinational logic.
The position of the inserted registers needs to be carefully chosen. The number of registers consumed varies by position; for example, if you consume 25 bits of registers at position a and 20 bits at position b, save where you can.
The earlier inserted registers made the delay of comb1 30ns and comb2 10ns. The system’s maximum operating frequency is determined by the longest path. This means that the cycle of the system’s maximum operating frequency cannot be less than 30ns. By inserting the pipeline earlier, we do not change the timing but use Retiming technology to equalize the delays between various combinational logics.
Resource Sharing
From a design perspective, the most common example is the counter. If one counter can achieve the task, there is no need to use two. The same logic between lower-level modules should try to use one circuit to reduce redundant designs.
Examples of sharing basic logic units include: area: adder > comparator > multiplexer, commonly referred to as add-compare-select.
A multiplier is essentially a full adder.
Thus, we have the sequence: select then compare, select then add, select then multiply.
Let’s illustrate with a diagram.
The most basic level of sharing is based on the sharing of basic components. Synthesis tools can perform a lot of automatic optimization, and during layout and routing, can further enhance resource utilization. Usually, optimization occurs within the same module, but if your tools are powerful enough, they can break module boundaries for optimization. Many modules can be disassembled and mixed together for routing, making module boundaries invisible from the backend. The routing optimization by tools is difficult for manual intervention.
Conclusion
The above is a classification from the perspective of basic circuit design and data path. As for control logic, simply put, it’s all about the state machine method. We will discuss this issue next time.
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