ARM processors are all RISC architecture, single-cycle operations, instruction pipelines, using load or store instructions to access memory.
ARM7 adopts the von Neumann architecture, 3 stage pipeline; ARM9 adopts Harvard architecture, 5 stage pipeline; Cortex-A15 adopts 13 stage pipeline.ARM after reset PC unconditionally points to 0x00000000.
MMU is the memory management unit of the ARM processor, CPU manages the control lines of virtual memory and physical memory, and is responsible for mapping virtual addresses to physical addresses, as well as providing hardware mechanisms for memory access authorization; the conversion from virtual address to physical address is done by looking up the page table, checking the TLB first when accessing memory, and if not found, checking the entire page table in memory.
MPU is the memory protection unit of the ARM processor, an optional component for protecting memory, allowing ARM processors to define 8 domains in a 4GB address space, controlling 8 instruction and 8 data memory regions.
AMBA is the Advanced Microcontroller Bus Architecture, an open standard for connecting and managing various functional modules in a system-on-chip; AMBA has evolved from 1.0 to 4.0 as of 2011, ARM7 uses AMBA1, while ARM9 uses AMBA2. The system bus and peripheral bus connected to AMBA are bridged, with slower external interfaces connected to the peripheral bus such as timers, parallel interfaces, and serial interfaces; while LCD controllers, DMA, interrupt controllers, and JTAG are on the system bus.
DMA is the direct memory access controller inside embedded chips, connected to the AMBA system bus, using it to transfer data can reduce processor load and lower system power consumption, DMA generally uses vector interrupts or nested vector interrupts to manage interrupts.
Magnetic Random Access Memory MRAM is a type of non-volatile memory, having the high-speed access capability of SRAM, and the high integration of DRAM;
Ferroelectric Memory FRAM has the non-volatility of read-only memory and the fast random read/write characteristics of random access memory, with low power consumption.
Flash Memory FLASH MEMORY is a long-life non-volatile memory, the most widely used read-only memory in recent years.
OTG stands for On-The-Go, enabling direct point-to-point communication between devices without a host.
Resistive Touch Screens are soft screens that use pressure sensitivity for control, simple structure, and low cost;
Capacitive Touch Screens are hard screens, complex structure, high cost, supporting multi-touch or swipe operations;
IIC is a serial half-duplex transmission bus standard, when no devices on the bus are in use, the pull-up resistors of SCL and SDA lines pull the level high, keeping them in high level. The first byte transmitted by the master device after starting the bus transmission operation is the address.IIC bus can connect multiple devices: the IIC device that actively initiates data transfer is the master device, otherwise it is a slave device, and there is no limit to the number of bytes transmitted each time.
USB 1.1/2.0 bus has 4 signal lines, using half-duplex differential mode to transmit signals and provide power, where d+ and d- are differential signal lines. It adopts a master-slave mode, with one host responsible for managing all USB device connections and deletions, initiating communication with USB devices.
Hardware Abstraction Layer HAL: It is located between the kernel operating system and the hardware, thus hiding the differences of hardware platforms and avoiding direct access of the operating system to hardware.
MP3 uses the MPEG-1 layer III algorithm for lossy compression encoding
CAN stands for Controller Area Network, using differential transmission, and CAN can form a multi-master multi-slave system, enabling multi-master communication. Its bus data frame consists of 7 different domains.
SPI interface is a synchronous serial peripheral interface, allowing embedded processors and peripheral devices to communicate and exchange data serially. In SPI, data is sent from the host’s shift register from left to right to the slave, while data in the slave is sent from right to left to the host, generally using 4 jumpers: SCK, MISO, MOSI, SSEL. One byte is sent in eight clock cycles.
Vxworks is currently recognized as the most real-time and reliable embedded real-time operating system. It charges a licensing fee based on the number of development licenses and also charges copyright fees based on the actual number of final products sold.
NAND Flash is accessed randomly by pages (rows), having significant advantages in capacity, lifespan, and cost. It is usually used as auxiliary storage.
NOR Flash is accessed randomly by bytes, used to store firmware in the system.
JTAG refers to the boundary scan testing method and TAP interface that meets the IEEE1149 standard, a general term for on-chip debugging technology. It is commonly used for debugging chips and circuit boards, and the standard specifies that the TAP interface has 5 signal lines: TCK, TMS, TDI, TDO, TRST.
RTC internal data registers are all 8 bit registers, storing corresponding BCD code values.
Single Kernel also known as macro kernel, has high application program production efficiency, occupies large memory space, uses many resources, lacks scalability, is difficult to maintain, has low predictability of task execution time, and low reliability; eliminating faults and adding new features requires recompilation.
Microkernel: compiles basic functions such as inter-process communication, low-level memory management, interrupt handling, and task management into a compact module. The kernel is small; interfaces are consistent; various functional modules are loosely coupled, only completing service functions, while system management functions are given to one or more privileged service programs; microkernel functionality is easy to expand, but the overhead caused by switching between functions is relatively large; based on client/server architecture, in microkernel structure operating systems, the inter-task communication mechanism – message mechanism is the foundation of the system, and various functions of the operating system are implemented by servers, providing services to clients.
Hard Real-Time Systems: If the execution time of a task exceeds the deadline, the total loss to the system is negative. The correctness of the operation of such real-time systems is closely related to their response time limits. Once the time limit is exceeded, it will lead to serious negative consequences, such as aircraft controllers and nuclear reaction processing devices.
ARM9-TDMI-S supports the Thumb instruction set, ARM v6 and later kernels automatically include T.D: supports on-chip debugging; M: embedded hardware multiplier; I: embedded ICE, supports on-chip breakpoints and debug points.S: and the integrated version, meaning the processor core is provided in source code form.
Big Endian Mode, means that the high byte of data is stored at the low address in memory, while the low byte of data is stored at the high address in memory, this storage mode is somewhat similar to processing data as a string in order: addresses increase from small to large, while data is placed from high to low; this is consistent with our reading habits.
Little Endian Mode, means that the high byte of data is stored at the high address in memory, while the low byte of data is stored at the low address in memory, this storage mode effectively combines the high and low of addresses with the weight of data bits, with high address parts having high weight and low address parts having low weight.
μC/OS-II is a small embedded operating system kernel, basically does not include device drivers and file systems, just a pure kernel, allowing interrupt nesting, with up to 255 layers of nesting; does not support time-slice scheduling; tasks are the basic scheduling unit of the operating system.
μC/OS-II is an open-source operating system, its upgraded version -iii is a commercial operating system; -ii has good scalability, supporting up to 64 tasks; the current version reserves 8 tasks for the system, so the user-written application can have at most 56 tasks, the idle task is the first task created by the system, with a priority of 63. Tasks are scheduled in a priority preemptive manner and each task has its own stack, it does not support time-slice scheduling, thus each priority is different. The operating system kernel schedules tasks under three conditions: all interrupt service routines have been completed, scheduling is not prohibited, and the highest priority task found in the ready task table has a higher priority than the currently running task.
S3C2410 memory control components: memory controller, bus controller, external master controller, NAND FLASH controller; the address space is a total of 1G, 8 BANKS, each BANK is 128M.IO and memory use unified addressing, unlike the X86 adopted IO mapped addressing (independent addressing) method, BANK0 can only be accessed by 16 bits and bus width, while all other BANKS can be accessed by 8, 16, or 32 bits.S3C2410 has separate 16KB size instruction CACHE and 16KB size data CACHE.
Stack Pointer SP uses register R13, link register LR uses register R14, program counter PC uses register R15 , R0-R15 are 32 bits, R0-R7 are used as general-purpose registers in any mode.
Other Knowledge
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arm11 after adopting cortex naming
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cortex -A -R -M are aimed at high-end applications, real-time control, and microprocessors respectively.
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Only GPIO can achieve parallel IO, SPI, UART, IIC all work serially
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rs232 uses negative logic transmission, while 485 uses differential signal transmission, rs485 has strong anti-interference ability.
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The protocols used in wireless local area networks are mainly IEEE 802.11a
g,
with a data transmission rate of up to 11-108Mb/s -
Most high-definition television image resolutions in China are 1920*1080 with an aspect ratio of 16:9
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When users install ADSL, they only need to configure an ADSL MODEM and a voice separator on the user side of the existing phone line, and the computer needs to install an Ethernet card
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Real-time operating systems have a time deviation for each task completion called jitter, the most important indicator of real-time performance is response time. That is, the time interval from the start of an event request to the completion of the task
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Currently, the digital cable television and satellite television digital video transmission encoding format is MPEG-2, while the latest format in internet video applications is H.264/MPEG-4 AVC
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linux operating system adheres to the general public license agreement under the GNU project, while the GNU developed programming language compiler is called GCC.
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nRESET indicates low-level reset, RESET indicates high-level reset
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Low-end systems mostly use 4/8 bit microcontrollers
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Keyboards used in embedded systems include linear keyboards and matrix keyboards
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Matrix keyboard interface: row scanning method and interrupt method to read the characteristic values of the keys of the keyboard interface.
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Typical embedded system hardware consists of embedded minimal hardware systems, forward channels, backward channels, human-computer interaction channels, and interconnection communication channels. The analog input interface and digital input interface form the forward channel.
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Applications call general functions and internal kernel functions through GLIBC.
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Code that cannot be divided during processing is called critical section, no interruptions are allowed. Execute OS_ENTER_CRITICAL() to disable interrupts.
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When a running task executes the timing delay function ostimedly(), the task will enter the suspended state, and once the scheduled time is reached, the task immediately enters the ready state.
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After the system is powered on, the first instruction executed by the CPU is the first instruction in the bootloader program, which is usually stored on some type of solid-state storage device
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The kernel manages tasks through a data structure called the task control block, when a task switch occurs, the working context of the task is saved to the task’s own stack.
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Network protocols provide access control to various network resources, and network drivers provide support for various network hardware.
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Mutex semaphores are usually used to solve priority inversion problems, and time flag groups are suitable for handling multi-event synchronization.
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The total number of times the system can handle tasks in a given time is called throughput.
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Microprocessors have word lengths: 4 8 16 32 64 instruction sets: RISC CISC system architectures: Harvard structure, von Neumann
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S3C2410 chip’s nGCS× connected to its CS pin (active low), then the first address for reading and writing the internal register of the AX88796 chip is: nGCS2 is【0x10000000】 nGCS3 is【0x18000000】 nGCS5 is【0x28000000】
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OS_Sched() task scheduling, OSTaskCreate() function for task creation, OSIntExit() interrupt-level scheduling, OSTickISR () for clock tick interrupt service routine, OSInit() used for initialization before creating tasks,
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CPSR is the current program status register, determining ARM processor working mode
N: Negative flag. If the signed number in the target register is negative, then N=1, otherwise N=0.
Z: Zero flag. If the number in the target register is 0, then Z=1, otherwise Z=0.
V: Overflow flag. If an error occurs during signed operation, then V=1, otherwise V=0.
I: IRQ interrupt disable bit.I=1 represents disabling IRQ interrupts, I=0 represents allowing IRQ interrupts.
F: FIQ interrupt disable bit.F=1 represents disabling FIQ interrupts, F=0 represents allowing FIQ interrupts.
28. GB2312 uses double bytes to store and transmit Chinese characters, GB18030 uses double bytes or four bytes
Unicode/UTF-8 uses three bytes, Unicode/UTF-16 uses double bytes variable-length encoding
29. The design of software components includes three parts: building the embedded web server environment, application webpage design, and GCI interface program design. When building the software platform, the system bootloader (Bootloader) must first be ported, then the Linux operating system and establish its root file system, and finally port the embedded Web server.
30. In user mode [M4 M3 M2 M1 M0]={1 0 0 0 0}. That is ORR R1,R0, 0x10|0xC0. Then through the instruction BL_main to guide the application main function main(). In the ARM9 architecture, it is stipulated that the exception vectors differ by 4 bytes, the reset exception vector address usually stores a branch instruction code. For the S3C2410 microprocessor, its bootloader also needs to complete disabling the watchdog component and disabling the external interrupt component, and set the stack pointer for each working mode
31. The logical composition of the hardware part of the embedded system and its connection with the external world
32. The relationship of the subsystems of the Linux kernel
