What is Embedded
IEEE (Institute of Electrical and Electronics Engineers) defines embedded systems as “devices used to control, monitor or assist the operation of machines and equipment”. The original text is: Devices Used to Control, Monitor or Assist the Operation of Equipment, Machinery or Plants).
Embedded systems are specialized computer systems that are part of a device or equipment. Typically, an embedded system consists of a control program stored in ROM on an embedded processor control board. In fact, all devices with digital interfaces, such as watches, microwaves, VCRs, and cars, use embedded systems. Some embedded systems also include operating systems, but most embedded systems implement the entire control logic with a single program.
Defined by their application objects, embedded systems are a combination of software and hardware and can also encompass mechanical and other auxiliary devices. The commonly accepted definition of embedded systems in China is: application-centered, based on computer technology, customizable in software and hardware, and specialized computer systems that meet strict requirements for functionality, reliability, cost, size, and power consumption.
An embedded system device generally consists of an embedded computer system and an execution device. The embedded computer system is the core of the entire embedded system, consisting of hardware layer, middleware layer, system software layer, and application software layer. The execution device, also known as the controlled object, can accept control commands issued by the embedded computer system and perform specified operations or tasks. The execution device can be very simple, like a tiny motor on a mobile phone that activates when the phone is in vibration mode; or it can be very complex, like the SONY Aibo robotic dog, which integrates multiple tiny control motors and various sensors to perform various complex actions and sense various status information.
Components of Embedded Systems
1. Hardware Layer: The hardware layer contains embedded microprocessors, memory (SDRAM, ROM, Flash, etc.), general device interfaces, and I/O interfaces (A/D, D/A, I/O, etc.). By adding power circuits, clock circuits, and memory circuits on top of an embedded processor, an embedded core control module is formed. The operating system and application programs can be solidified in ROM.
2. Middleware Layer: The middleware layer, also known as the Hardware Abstract Layer (HAL) or Board Support Package (BSP), separates the upper software from the lower hardware, allowing the system’s lower-level drivers to be hardware-independent. Upper-level software developers do not need to worry about the specifics of the lower hardware and can develop based on the interfaces provided by the BSP layer. This layer generally includes the initialization of relevant lower-level hardware, data input/output operations, and hardware device configuration functions. In practice, BSP is a software layer that exists between the operating system and the lower hardware, including most of the software modules that are closely related to the hardware in the system. Designing a complete BSP requires completing two parts of work: the BSP functions for the hardware initialization of the embedded system and designing hardware-related device drivers.
3. System Software Layer: The system software layer consists of real-time multitasking operating systems (RTOS), file systems, graphical user interfaces (GUI), network systems, and general component modules. RTOS serves as the foundation and development platform for embedded application software.
(1) Definition: A system that can complete its functions and respond to external or internal events, both synchronously and asynchronously, within specified or determined time.
(2) Difference: General systems typically pursue average response time and user convenience, while real-time systems primarily consider the worst-case system behavior.
(3) Characteristics: Time constraints, predictability, reliability, and interactivity with the external environment.
(4) Hard Real-Time: Refers to applications where timing requirements must be fully met; otherwise, it may cause significant safety incidents or even major loss of life and property and ecological damage, such as in aerospace and military applications.
(5) Soft Real-Time: Refers to applications that have timing requirements, but occasional violations of real-time tasks do not severely impact system operation and environment, such as monitoring systems and real-time information collection systems.
(6) Constraints of tasks include: time constraints, resource constraints, execution order constraints, and performance constraints.
Scheduling of Real-Time Systems
(1) Scheduling: The entire process of determining when and where each task will execute, given a set of real-time tasks and system resources.
(2) Preemptive Scheduling: Generally priority-driven scheduling, such as uCOS. Advantages include good real-time performance and fast response, and relatively simple scheduling algorithms can ensure high-priority tasks meet their time constraints; disadvantages include frequent context switches.
(3) Non-Preemptive Scheduling: Generally time-slice allocation scheduling, which does not allow tasks to be interrupted during execution. Once a task occupies the processor, it must complete execution or voluntarily relinquish it, such as WinCE. Advantages include fewer context switches; disadvantages include low effective resource utilization of the processor and poor schedulability.
(4) Static Table Driven Strategy: The system generates a runtime schedule based on the time constraints and relationships of tasks before running, indicating the start time and duration of each task.
(5) Priority Driven Strategy: Determines the execution order of tasks based on their priority levels.
(6) Classification of Real-Time Tasks: Periodic tasks, sporadic tasks, and aperiodic tasks.
(7) General Structural Model of Real-Time Systems: Data acquisition tasks achieve sensor data collection, data processing tasks process the collected data, and send the processed data to the execution agency management tasks for control execution.
Embedded Microprocessor Architecture
(1) Von Neumann Architecture: Programs and data share a single memory space, with program instruction storage addresses and data storage addresses pointing to different physical locations in the same memory, using a single address and data bus, with the same width for both programs and data. For example: 8086, ARM7, MIPS…
(2) Harvard Architecture: Programs and data are two independent memories, each with independent addressing and access, a memory structure that separates program storage from data storage. For example: AVR, ARM9, ARM10…
(3) Comparison of CISC and RISC Characteristics.
The time P required for a computer to execute a program can be calculated using the following formula:
I: The number of instructions in the machine after compiling the high-level language program.
CPI: The average number of cycles required to execute each instruction.
T: The time for each machine cycle.
(4) The Idea of Pipelining: In a CPU, the serial execution process of an instruction is transformed into overlapping execution of several instruction subprocesses in the CPU.
Throughput: The number of results processed by the pipeline in a unit time. If the times of subprocesses in the pipeline are different, the throughput should be the reciprocal of the longest subprocess time.
Establishment Time: The time from when the pipeline starts working until it reaches maximum throughput. If m subprocesses have the same duration, t, then the establishment time T=mt.
(6) Byte Order of Information Storage
A. Memory unit: Byte (8 bits)
B. Word length determines the addressing capability of the microprocessor, that is, the size of the virtual address space.
C. The virtual address space of a 32-bit microprocessor is 2^32, or 4GB.
D. Little-endian byte order: Low byte is at low address in memory, high byte is at high address in memory.
E. Big-endian byte order: High byte is at low address in memory, low byte is at high address in memory.
F. The storage order of network devices depends on the data link layer in the OSI model.
Fundamentals of Logic Circuits
(1) Logic circuits are classified into: combinational logic circuits and sequential logic circuits, based on whether they have storage functions.
(2) Combinational Logic Circuits: The output of the circuit at any moment depends only on the input signals at that moment, regardless of the state of the circuit before the input signals acted on it. Common logic circuits include decoders and multiplexers.
(3) Sequential Logic Circuits: The output of the circuit at any moment depends not only on the input at that moment but also on the state of the circuit at that moment. Therefore, sequential circuits must include memory elements. Flip-flops are the basic building blocks of sequential logic circuits. Common sequential logic circuits include registers and counters.
(4) Truth tables, Boolean algebra, De Morgan’s laws, and concepts of gate circuits.
(5) NOR (Not OR) and NAND (Not AND) gate circuits are called universal gate circuits, capable of implementing any logical function.
(6) Decoder: A combinational logic network with multiple inputs and outputs. For each n-bit binary code input, at most one output among m outputs is valid. When m=2^n, it is a full decoder; when m<2^n, it is a partial decoder.
(7) Due to the low output current of integrated circuits at high levels and relatively high output current at low levels, when directly driving LEDs with integrated gate circuits, it is often preferable to use a low-level driving method. LCD seven-segment character displays utilize the different optical properties of liquid crystals with and without an external electric field to display characters.
(8) Clock signals are the foundation of sequential logic, determining when to update the state in logic units. Synchronization is a major constraint in clock-controlled systems.
(9) When selecting flip-flops, the triggering method is a necessary consideration. There are two types of triggering methods:
Level-triggered: has a simple structure and is commonly used to form registers.
Edge-triggered: has strong resistance to data line interference and is commonly used to form registers, counters, etc.
Bus Circuits and Signal Driving
(1) A bus is a collection of various signal lines, serving as a common pathway for transmitting data, addresses, and control information between components in an embedded system. At any given time, each path can transmit one binary signal. Depending on the type of information transmitted by the bus, it can be classified into: data bus (DB), address bus (AB), and control bus (CB).
(2) Main parameters of the bus:
Bus bandwidth: The amount of data that can be transmitted over the bus in a given time, usually expressed in MByte/s.
Bus width: The number of bits (bit) that can be transmitted simultaneously by the bus, commonly referred to as the concept of bus width (e.g., 32-bit, 64-bit). The wider the bus, the greater the data transfer rate per second, meaning the wider the bus bandwidth.
Bus frequency: The working clock frequency measured in MHz; the higher the working frequency, the faster the bus operates, meaning the wider the bus bandwidth.
Bus bandwidth = Bus width × Bus frequency / 8, measured in MBps.
Common buses include ISA bus, PCI bus, IIC bus, SPI bus, PC104 bus, and CAN bus, etc.
(3) Only devices with tri-state outputs can connect to the data bus; commonly used tri-state gates are output buffers.
(4) When the load connected to the bus exceeds its load capacity, a buffer or driver must be added between the bus and the load; the most commonly used is a tri-state buffer, which serves to drive and isolate.
(5) Using bus multiplexing technology can realize the sharing of data and address buses. However, it brings two issues:
A. It requires additional external circuits to decouple the bus signals, such as address latch circuits.
B. The bus speed is relatively lower compared to non-multiplexed bus systems.
(6) Two types of bus communication protocols: synchronous and asynchronous.
(7) The solution to the bus arbitration problem is based on the concept of priority (priority).
Level Conversion Circuits
(1) Digital integrated circuits can be divided into two major categories: bipolar integrated circuits (TTL) and metal-oxide-semiconductor (MOS).
(2) CMOS circuits are widely used due to their very low static power consumption, high operating speed, and strong anti-interference capability.
(3) The solution to the interface difficulties between TTL and CMOS circuits is to connect a pull-up resistor R between the output of the TTL circuit and the power supply. The value of pull-up resistor R is determined by the high-level output leakage current IOH of TTL; different series of TTL should use different R values.
Fundamentals of Information Representation and Computation in Embedded Systems
(1) Carry Counting System and Conversion: This is relatively simple and should be mastered for possible exam questions.
(2) Representation of numbers in computers: Source code, one’s complement, and two’s complement.
The one’s complement of a positive number is the same as its source code; the one’s complement of a negative number is the source code of that number with all bits inverted except for the sign bit.
The two’s complement of a positive number is the same as its source code; the two’s complement of a negative number is the one’s complement of that number plus one.
For example, the source code of -98 is: 11100010B
One’s complement: 10011101B
Two’s complement: 10011110B
(3) Fixed-point representation: The position of the decimal point is fixed by convention.
Floating-point representation: The position of the decimal point is variable, consisting of the mantissa and exponent parts.
Any binary N can be written as: N=2^P×S. S is the mantissa, P is the exponent.
(4) Representation of Chinese characters: Understand the conversion between GB2318-80 Chinese standard code and internal code.
(5) Quantization parameters in speech coding (may involve simple calculation problems)
Sampling frequency: The number of samples taken in one second, reflecting the size of the intervals between sampling points.
The upper limit of human hearing is 20kHz, so a sampling frequency above 40kHz is sufficient to satisfy human hearing.
The sampling frequency used in CD recordings is 44.1kHz.
Measurement accuracy: The quantization levels of samples; currently, standard sampling levels are 8-bit and 16-bit.
Number of channels: Mono and stereo. Stereo requires twice the storage space.
(1) Based on the function of the code group, it can be divided into error detection codes and error correction codes. Error detection codes can automatically detect errors, such as parity check codes; error correction codes can not only detect errors but also automatically correct them, such as cyclic redundancy check codes.
(2) Parity check codes, Hamming codes, cyclic redundancy check codes (CRC).
Metrics for Embedded Systems
(1) Performance indicators: divided into component performance indicators and comprehensive performance indicators, mainly including: throughput, real-time performance, and various utilization rates.
(2) Reliability and safety
Reliability is the most important and prominent basic requirement of embedded systems, ensuring that an embedded system can operate normally, generally measured by the Mean Time Between Failures (MTBF).
(3) Maintainability: Generally represented by the Mean Time To Repair (MTTR).
(6) Environmental adaptability
Cost-performance ratio includes not only the direct purchase price of the embedded system but also installation costs, several years of operating and maintenance costs, and software rental fees.
Evaluation Methods of Embedded Systems: Measurement and Modeling Methods
(1) The measurement method is the most direct and basic method, requiring the resolution of two issues:
A. Determine the system parameters to be measured based on the research purpose.
B. Select the tools and methods for measurement.
(2) There are two methods of measurement: sampling method and event tracking method.
(3) The modeling method is divided into analytical modeling and simulation modeling. Analytical modeling uses mathematical equations to characterize the system model, while simulation modeling uses the operation of simulation programs to dynamically express the state of embedded systems and conduct statistical analysis to derive performance indicators.
(4) The most commonly used analytical model is the queuing model, which includes three parts: input flow, queuing rules, and service organization.
(5) Evaluating a system using a model requires resolving three issues: designing the model, solving the model, and calibrating and validating the model.
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(1) Flash memory is a type of non-volatile memory that can be divided into NOR Flash and NAND Flash based on structural differences.
(2) Characteristics of Flash memory:
A. Block structure: Physically divided into several blocks, with blocks being independent of each other.
B. Erase-before-write: The write operation of Flash can only change data bits from 1 to 0, not from 0 to 1, so before writing to the memory, an erase operation must be performed to initialize the pre-written data bits to 1. The minimum unit of the erase operation is a block, not a single byte.
C. Operation instructions: To perform a write operation, it must enter a series of special instructions (NOR Flash) or complete a timing sequence (NAND Flash) to write data.
D. Bit inversion: Due to the inherent characteristics of Flash, one or more data errors may occur during read and write. Bit inversion cannot be avoided and can only be processed later by other means.
E. Bad blocks: Once a block is damaged, it cannot be repaired. The results of operations on damaged blocks are unpredictable.
(3) Characteristics of NOR Flash:
Application programs can run directly in flash memory without needing to read the code into the system RAM for execution. NOR Flash has very high transmission efficiency, which is very cost-effective for small capacities of 1MB to 4MB, but its low write and erase speeds significantly affect its performance.
(4) Characteristics of NAND Flash
Can achieve very high density units, allowing for high storage density, and also has fast write and erase speeds, which is why all USB drives use NAND Flash as the storage medium. The difficulty in applying NAND Flash lies in the need for special system interfaces.
(5) Differences between NOR Flash and NAND Flash:
A. NOR Flash has slightly faster read speeds than NAND Flash.
B. NAND Flash’s erase and write speeds are much faster than those of NOR Flash.
C. NAND Flash has poor random read capabilities and is suitable for large amounts of continuous data reading.
D. NOR Flash has SRAM interfaces, allowing sufficient address lines for easy access to each byte within it. NAND Flash shares an 8-bit bus for addresses, data, and commands (some products use 16 bits), requiring complex I/O interfaces for serial access to data during each read and write operation.
E. NOR Flash typically has a smaller capacity, usually between 1MB and 8MB; NAND Flash is only used in products with over 8MB capacity. Therefore, NOR Flash is mainly used in code storage media, while NAND Flash is used for data storage.
F. The maximum erase/write cycles for each block in NAND Flash is one million times, while for NOR Flash, it is one hundred thousand times.
G. NOR Flash can be directly connected like other memory types and can run code directly on it; NAND Flash requires special I/O interfaces, necessitating the writing of driver programs before other operations can continue. Designers must never write to bad blocks, meaning virtual mapping must always occur on NAND Flash.
H. NOR Flash is used in fields requiring high reliability for data storage, communication products, and network processing, referred to as code flash; NAND Flash is used in fields requiring high storage capacity, such as MP3 players, storage cards, and USB drives, referred to as data flash.
(1) Characteristics of SRAM:
SRAM stands for Static Random Access Memory, which maintains a value as long as power is supplied. It has no refresh cycle and is composed of flip-flops, making it low in integration; each SRAM storage unit consists of 6 transistors, resulting in a higher cost. It has a relatively high speed and is commonly used in cache memory.
Typically, SRAM has four pins:
CE: Chip select signal, active low.
R/W: Read/write control signal.
ADDRESS: A group of address lines.
DATA: A group of bidirectional signal lines used for data transmission.
(2) Characteristics of DRAM:
DRAM stands for Dynamic Random Access Memory. It is a type of semiconductor memory that stores data in the form of electric charges. Each storage unit consists of a transistor and a capacitor, with data stored in the capacitor. The capacitor loses charge due to leakage, making DRAM devices unstable. It must be refreshed regularly to retain data in memory.
The interface of DRAM is relatively complex, typically having the following pins:
CE: Chip select signal, active low.
R/W: Read/write control signal.
RAS: Row address strobe signal, usually connected to the high-order part of the address.
CAS: Column address strobe signal, usually connected to the low-order part of the address.
ADDRESS: A group of address lines.
DATA: A group of bidirectional signal lines used for data transmission.
(3) Characteristics of SDRAM:
SDRAM stands for Synchronous Dynamic Random Access Memory. Synchronous means that memory operation requires a synchronous clock; internal command transmission and data transmission are based on it; dynamic means that the memory array requires constant refreshing to ensure data is not lost. It typically operates at a main frequency of 133MHz.
(4) Characteristics of DDRAM:
DDRAM stands for Double Data Rate Synchronous Dynamic Random Access Memory, also known as DDR. DDRAM is based on SDRAM technology; SDRAM transmits data once per clock cycle, while DDR memory transmits data twice per clock cycle, once on the rising edge and once on the falling edge of the clock. At a main frequency of 133MHz, DDR memory can achieve a bandwidth of 133×64b/8×2=2.1GB/s.
3. Hard Drives, Optical Discs, CF Cards, SD Cards
4. GPIO Principles and Structures
GPIO is the most basic form of I/O, consisting of a set of input or output pins. Some GPIO pins can be programmed to change their working direction, usually having two control registers: data register and data direction register. The data direction register sets the direction of the port. If a pin is set to output, the data register controls the state of that pin. If the pin is set to input, the state of this input pin is controlled by the logic circuit layer on the pin.
(1) A/D converters are circuits that convert analog electrical signals into digital signals. There are many methods for A/D conversion, commonly used methods include counting method, dual integration method, and successive approximation method.
(2) Counting A/D Conversion Method
The main components of its circuit include: comparator, counter, D/A converter, and standard voltage source.
The working principle is simply that there is a counter that starts counting from 0, increasing by 1 each time. Each increment serves as input for the D/A converter, which generates a comparison voltage VO to compare with the input analog voltage VIN. If VO is less than VIN, the counting continues until VO exceeds VIN, at which point the accumulated value of the counter is the output value of the A/D converter.
This conversion method is simple but relatively slow, especially when the analog voltage is high; the conversion speed becomes even slower. For example, for an 8-bit A/D converter, if the input analog value is at maximum, the counter must count from 0 to 255, performing 255 D/A conversions and voltage comparisons to complete the conversion.
(3) Dual Integration A/D Conversion Method
The main components of its circuit include: integrator, comparator, counter, and standard voltage source.
The working principle is that the circuit first integrates the input voltage to be measured for a fixed time, then performs a reverse integration with a standard voltage at a fixed slope until it returns to the starting value. Because it uses a fixed slope, the time taken for reverse integration is proportional to the value of the input analog voltage; the larger the input analog voltage, the longer the time taken to return to the starting value. By measuring the time taken for reverse integration with a standard high-frequency clock pulse, the corresponding digital value of the input analog voltage can be obtained, thus completing the A/D conversion.
This method has strong resistance to industrial frequency interference and high conversion accuracy, but the conversion speed is slow, typically with a conversion frequency of less than 10Hz, mainly used in digital testing instruments, temperature measurements, etc.
(4) Successive Approximation A/D Conversion Method
The main components of its circuit include: comparator, D/A converter, successive approximation register, and reference voltage source.
The working principle is essentially a binary search method, similar to the use of a balance scale. During A/D conversion, the D/A converter increases the conversion bit from high to low, generating different output voltages to compare the input voltage with the output voltage. The highest bit is set to 1, which is equivalent to comparing half of the reference voltage with the input voltage; if the input voltage is less than half of the reference voltage, the highest bit is set to 0, otherwise it is set to 1. Next, the second highest bit is set to 1, which is equivalent to performing a binary search within half of the range, and so on, approaching the target.
This method is fast, with high conversion accuracy; for an N-bit A/D converter, only M clock pulses are required to complete the conversion, making it the most widely used conversion method for measuring transitions lasting dozens to hundreds of microseconds.
(5) Important Indicators for A/D Conversion (may involve some simple calculations)
A. Resolution: Reflects the A/D converter’s ability to respond to small changes in input, usually represented by the voltage level corresponding to the least significant bit (LSB) of the digital output. An N-bit A/D converter can reflect 1/2^n full-scale analog input voltage.
B. Range: The range of analog input voltage that can be converted, divided into unipolar and bipolar types.
C. Conversion time: The time required to complete one A/D conversion, the reciprocal of which is the conversion rate.
D. Accuracy: Accuracy and resolution are two different concepts; even if the resolution is high, accuracy may still be insufficient due to temperature drift, linearity, etc. Accuracy can be expressed in absolute and relative terms. Absolute accuracy is represented by the fractional value of the least significant bit (LSB) of the digital quantity; relative accuracy is expressed as a percentage of the full-scale analog voltage.
For example, with a full-scale of 10V and a 10-bit A/D chip, if its absolute accuracy is ±1/2 LSB, then its minimum effective bit LSB quantization unit is: 10/1024=9.77mV, its absolute accuracy is 9.77mV/2=4.88mV, and its relative accuracy is: 0.048%.
(1) D/A converters convert digital quantities into analog quantities.
(2) In integrated circuits, T-type networks are usually used to convert digital quantities into analog currents, which are then converted into analog voltages by operational amplifiers. D/A conversion actually requires these two steps.
(3) Types of D/A converters:
A. Voltage output type: commonly used as high-speed D/A converters.
B. Current output type: generally used with external operational amplifiers.
C. Multiplying type: can be used as modulators and for digitally attenuating input signals.
(4) Main indicators of D/A converters: resolution, establishment time, linearity, conversion accuracy, temperature coefficient.
(1) Two forms of keyboards: linear keyboard and matrix keyboard.
(2) Two methods are commonly used to identify closed keys on the keyboard: row scanning method and row inversion method.
(3) The row scanning method is the commonly used identification method for matrix keyboard keys, which proceeds in two steps:
A. Identify which column’s key is pressed: set all row lines to low level, and check whether the column lines are low. If any column line is low, it indicates that a key in that column is pressed; otherwise, there is no key pressed.
B. If a key is pressed in a column, identify which row is pressed: set each row to low level one by one while keeping the others at high level, checking for changes in the columns. If a column’s level changes to low, it can determine which key is pressed at the intersection of that row and column.
(1) The basic principle of LCD is to control the passage of light through different liquid crystal units by supplying power to them to achieve display purposes.
(2) There are two methods for providing light sources for LCDs: projection type and reflection type. The LCD display of a laptop is of the projection type, where there is a light source behind the screen, so external light sources are not needed. Generally, LCDs used on microcontrollers are of the reflection type, requiring an external power source and relying on reflected light to operate. Electroluminescence (EL) is one way for liquid crystal displays to provide light sources.
(3) According to the driving method of liquid crystals, common LCDs can be divided into three types: Twisted Nematic (TN), Super Twisted Nematic (STN), and Thin Film Transistor (TFT).
(4) There are two types of LCDs available on the market: LCD display modules with driver circuits that can be driven by bus methods; and LCD displays without driver circuits that use controller scanning methods.
(5) Usually, when the LCD controller operates, it requests the bus through DMA, directly reading data from the specified address (display buffer) in SDRAM; this data is converted into the liquid crystal screen scanning data format by the LCD controller and directly drives the liquid crystal display.
(6) The VGA interface is essentially an analog interface, generally using a unified 15-pin interface, including 2 NC signals, 3 display data bus lines, 5 GND signals, 3 RGB color components, 1 horizontal sync signal, and 1 vertical sync signal. The voltage level standard for color components is defined by the EIA RS343 standard.
9. Touch Screen Interface
(1) Touch screens can be classified into surface acoustic wave screens, capacitive screens, resistive screens, and infrared screens based on their working principles.
(2) Touch screen control uses specialized chips, such as ADS7843.
(1) The basic principle: The data input from the microphone is decoded by the audio codec to complete A/D conversion; the decoded audio data is sent to the DSP or CPU for processing through the audio controller, and then the data is sent to the audio encoder, converted back to analog by D/A conversion, and output by the speaker.
(2) There are various formats for digital audio, the three most common being:
A. Using digital audio (PCM): The data format used by CDs or DVDs, with a sampling frequency of 44.1kHz. When the accuracy is 16 bits, the PCM audio data rate is 1.41Mb/s; at 32 bits, it is 2.42 Mb/s. A 700MB CD can store about 60 minutes of 16-bit PCM formatted music.
B. MPEG Layer 3 Audio (MP3): The audio format used by MP3 players, with stereo MP3 data rates ranging from 112kb/s to 128kb/s.
C. ATSC Digital Audio Compression Standard (AC3): The digital audio encoding standard for digital TV, HDTV, and movies, with stereo AC3 encoded data rates of 192kb/s.
(3) IIS is a commonly used serial audio digital interface for audio data encoding or decoding. The IIS bus only processes sound data, while other control signals must be transmitted separately. IIS uses three serial buses: data line SD, word select line WS, and clock signal line SCK.
(4) When the data field widths of the sender and receiver differ, the sender does not consider the receiver’s data field width. If the sender’s data field is smaller than the system field width, it is padded with 0 at the lower bits; if the sender’s data width exceeds the receiver’s width, the excess LSB portion is truncated. The word select WS is used to select the left or right channel, with WS=0 indicating the left channel and WS=1 indicating the right channel. Additionally, WS allows the receiving device to store the previous byte and prepare to receive the next byte.
(1) Serial communication refers to the transmission of data one bit at a time. Compared to parallel communication, serial communication has fewer transmission lines and lower costs, making it particularly suitable for long-distance transmission; however, it is slower.
(2) There are three basic communication modes for serial data transmission: simplex, half-duplex, and full-duplex.
(3) Serial communication can be divided into two types based on information format: synchronous communication and asynchronous communication.
A. Asynchronous transmission: Each character is treated as independent information for transmission, sent according to a fixed and predetermined timing, but the timing between characters depends on the arbitrary timing between characters. In asynchronous communication, each character is transmitted as a frame, with the start bit used for synchronization. The time interval between each frame is fixed, while the time intervals between adjacent frames are not fixed.
B. Synchronous transmission: In synchronous mode, not only are characters synchronized, but the timing between characters is also synchronized. Synchronous mode transmits many characters in a character block, adding 1-2 synchronization characters before each block of information, followed by appropriate error detection data before transmission.
(4) Asynchronous communication must adhere to three regulations:
A. Character format: Start bit + data + parity bit + stop bit (the parity bit can be omitted), with low bits transmitted first.
B. Baud rate: The number of bits transmitted per second.
C. Parity bit: Odd/even parity.
a. Odd parity: The parity bit is added so that there are an odd number of “1s” in the character.
b. Even parity: The parity bit is added so that there are an even number of “1s” in the character.
(5) The electrical characteristics of RS-232C are negative logic.
A. On TxD and RxD: Logic 1 is -3V to -15V, and logic 0 is 3V to 15V.
B. On control lines such as TES, CTS, DTR, DCD: the effective signal (ON state) is 3V to 15V, while the invalid signal (OFF state) is -3V to -15V.
(6) The level conversion between TTL standards and RS-232C standards is achieved using integrated circuit RS232.
(7) RS-422 Serial Communication Interface
A. RS-422 is a unidirectional, balanced transmission specification for single machine transmission and multiple machine reception, capable of transmission rates up to 10Mb/s.
B. RS-422 employs differential transmission, also known as balanced transmission, using a pair of twisted wires.
C. RS-422 requires a terminal resistor, whose resistance value should be approximately equal to the characteristic impedance of the transmission cable.
(8) RS-485 Serial Bus Interface
A. RS-485 is a standard established based on RS-422, adding multi-point, bidirectional communication capabilities, with communication distances ranging from dozens of meters to thousands of meters.
B. RS-485 transceivers use balanced transmission and differential reception, providing the ability to suppress common-mode interference.
C. RS-485 requires two terminal resistors. Terminal resistors may not be needed for short-distance transmission (under 300m).
(1) The data transmission rate of parallel interfaces is 8 times faster than that of serial interfaces, with a standard parallel interface data transmission rate of 1Mb/s, commonly used to connect printers, scanners, etc., and hence also referred to as printer ports.
(2) Parallel interfaces can be divided into SPP (Standard Parallel Port), EPP (Enhanced Parallel Port), and ECP (Extended Parallel Port).
(3) Parallel buses are divided into standard and non-standard categories. Common standard parallel buses include IEEE 488 bus and ANSI SCSI bus. The MXI bus is a high-performance non-standard general-purpose multi-user parallel bus.
(1) The PCI bus is a high-performance 32-bit and 64-bit bus that multiplexes addresses and data, serving as the interconnection mechanism between microprocessors and peripheral control components and peripheral expansion boards.
(2) In terms of data width, PCI defines a 32-bit data bus, which can be expanded to 64 bits. In terms of bus speed, there are two types: 33MHz and 66MHz.
(3) Compared to the ISA bus, the PCI bus multiplexes the address bus and the data bus, supporting plug-and-play, interrupt sharing, and other features.
(1) The main characteristics of the USB bus:
A. Simple to use, plug-and-play.
B. Every USB system has a host, and this USB network can connect up to 127 devices at most.
C. Wide application range, supporting multiple devices to operate simultaneously.
D. Low-cost cables and connectors, using a unified 4-pin plug.
E. Strong error correction capability.
F. Low protocol overhead leads to high bus performance, suitable for the development of low-cost peripherals.
G. Supports multiple data streams and message streams between the host and devices, and supports both synchronous and asynchronous transmission types.
H. Bus powered, capable of providing 5V/100mA of power to devices.
(2) The USB system consists of three parts: USB host, USB device, and USB interconnect.
(3) The USB bus supports three data transmission rates: high-speed signaling rate of 480Mb/s; full-speed signaling rate of 12Mb/s; low-speed signaling rate of 1.5Mb/s.
(4) USB bus cables consist of four wires: a pair of twisted signal wires and a pair of power wires.
(5) USB is a polling bus, where the host initiates all data transmissions. The peripherals connected to USB share the USB bandwidth through a token-based protocol scheduled by the host.
(6) Most bus transactions involve the transmission of three packets:
A. Token Packet: Indicates what transaction to perform on the bus, the USB device to address, and the direction of data transfer.
B. Data Packet: Transmits data or indicates that there is no data to transmit.
C. Handshake Packet: Indicates whether the transmission was successful.
(7) The USB data transmission model between the host and device endpoints is referred to as a pipe. There are two types of pipes: stream and message. Message data has a structure defined by USB, while stream data does not.
(8) The transaction scheduling table allows for flow control of certain stream pipes, adjusting the data transmission rate at the hardware level using NAK (negative acknowledgment) handshake signals to prevent buffer overflow or underflow.
(9) The most significant feature of USB devices is plug-and-play.
(10) Working principle: When a USB device is inserted into a USB endpoint, the host communicates with the device’s endpoint 0 using the default address 0. During this process, the host issues a series of standard requests to obtain descriptors, gaining all the information of interest about the device, thereby understanding the device’s status and how to communicate with it. The host then issues a Set Address request to assign a unique address to the device. After that, the host communicates with the device using the assigned address, no longer using the default address 0.
(1) SPI is a synchronous protocol interface, where all transmissions are referenced to a common clock generated by the host, and receiving devices use the clock to synchronize the reception of the serial bit stream.
(2) When multiple devices are connected to the same SPI interface, the host selects the slave device using the slave device’s chip select pin.
(3) SPI mainly uses four signals: Master Out/Slave In (MOSI), Master In/Slave Out (MISO), Serial Clock (SCLK), and Slave Select (CS).
(4) Both the master and slave devices contain a serial shift register; the master initiates a data transfer by writing a byte into its SPI serial register. The register sends the byte to the slave via the MOSI signal line, and the slave returns the contents of its shift register to the master via the MISO signal line, thus exchanging the contents of both shift registers.
(5) The write and read operations between the master and slave are completed synchronously, making SPI a very efficient protocol.
(6) If only a write operation is performed, the master can ignore the received byte; conversely, if the master wants to read a byte from the slave, it must send an empty byte to trigger the slave’s transmission.
(1) The IIC bus is a high-performance multi-master bus with bus arbitration and synchronization functions for high-speed and low-speed devices.
(2) The IIC bus requires two lines: Serial Data Line (SDA) and Serial Clock Line (SCL).
(3) Each device on the bus has a unique address for identification, and each device can act as a sender or receiver (depending on its function).
(4) The IIC bus has four operating modes: master send, master receive, slave send, and slave receive.
(5) There are three types of signals during data transmission on the IIC bus:
A. Start signal: When SCL is low, SDA jumps from high to low.
B. Stop signal: When SCL is low, SDA jumps from low to high.
C. Acknowledge signal: The receiver sends a specific low signal to the sender after receiving 8 bits of data during the ninth pulse.
(6) After the master device sends a start signal, it immediately sends a slave address to notify the slave device with which it will communicate. One byte of address includes 7 bits of address information and 1 bit of transmission direction indication; if the 7th bit is 0, it indicates a write operation; if it is 1, it indicates a read operation.
(7) Each byte transmitted on the SDA line is 8 bits long, and there is no limit to the number of bytes transmitted during each transmission. The first byte after the start signal is the address field, and each transmission byte is followed by an acknowledgment bit (ACK); the most significant bit (MSB) of the serial data is sent first.
(8) If the data receiver can no longer accept more data, it can interrupt the transmission by keeping SCL low, forcing the data sender to wait until SCL is released again. This allows for synchronization between high-speed and low-speed devices.
(9) The working process of the IIC bus: SDA and SCL are both bidirectional. When idle, SDA and SCL are both high; only when SDA goes low, followed by SCL going low, does the data transmission on the IIC bus begin. Each bit transmitted on the SDA line is sampled on the rising edge of SCL and must remain valid until SCL goes low again, after which SDA transmits the next bit before SCL goes high again, indicating the end of data transmission.
(1) The most commonly used Ethernet protocol is the IEEE802.3 standard.
(2) Transmission encoding (06 and 07 both have): Manchester encoding and differential Manchester encoding.
A. Manchester encoding: Each bit has a voltage level transition in the middle; a transition from high to low indicates “0”, while a transition from low to high indicates “1”.
B. Differential Manchester encoding: Each bit has a voltage level transition in the middle; the presence or absence of a transition at the start of each code element indicates “0” or “1”, respectively.
(3) Comparatively, Manchester encoding is simpler, while differential Manchester encoding provides better noise suppression performance.
(4) Ethernet data transmission characteristics:
A. All data bits are transmitted starting from the low bit, using Manchester encoding for the bit stream.
B. Ethernet is based on a collision detection bus multiplexing method, executed automatically by hardware.
C. The length of the transmitted data includes the destination address (DA) + source address (SA) + type field (TYPE) + data segment (DATA) + padding bits (PAD), with a minimum length of 60B and a maximum length of 1514B.
D. Generally, Ethernet cards can receive data from three types of addresses: broadcast address, multicast address, and their own address.
E. The physical address of any two network cards is different; it is unique in the world, assigned by a specialized organization.
(5) There are two implementation methods for embedded Ethernet interfaces:
A. Embedded processor + network card chip (e.g., RTL8019AS, CS8900, etc.)
B. Processor with Ethernet interface.
(6) TCP/IP is a layered protocol, consisting of: physical layer, data link layer, network layer, transport layer, and application layer. Each layer implements a specific function, corresponding to one or more transmission protocols, with each layer functioning independently as a data packet relative to its lower layer. The protocols at each layer are as follows:
A. Application Layer: BSD Sockets.
B. Transport Layer: TCP, UDP.
C. Network Layer: IP, ARP, ICMP, IGMP.
D. Data Link Layer: IEEE802.3 Ethernet MAC.
E. Physical Layer: Binary bit stream.
(7) ARP (Address Resolution Protocol)
A. The network layer uses a 32-bit address to identify different hosts (i.e., IP addresses), while the link layer uses a 48-bit physical address (MAC) to identify different Ethernet or token ring interfaces.
B. The function of ARP: to achieve conversion from IP address to corresponding physical address.
(8) ICMP (Internet Control Message Protocol)
A. It is used at the IP layer to exchange error messages and other important control information with other hosts or routers.
B. ICMP messages are transmitted within IP packets.
C. Network diagnostic tools ping and traceroute are actually ICMP protocols.
(9) IP (Internet Protocol)
A. IP operates at the network layer and is the core protocol of the TCP/IP protocol suite.
B. All TCP, UDP, ICMP, and IGMP data are transmitted in the format of IP packets.
C. TTL (Time To Live field): Specifies the lifespan of an IP packet (the number of routers a packet can pass through).
D. IP provides unreliable, connectionless packet delivery services, being efficient and flexible.
a. Unreliable: It cannot guarantee that packets will reach their destination successfully; any required reliability must be provided by the upper layer (e.g., TCP). In the event of an error, IP has a simple error handling algorithm—discard the packet and send an ICMP message back to the source.
b. Connectionless: IP does not maintain any state information about subsequent packets. Each packet’s handling is independent. IP packets may be received out of order.
(10) TCP (Transmission Control Protocol)
TCP is a connection-oriented, reliable transport layer protocol that provides high reliability end-to-end data communication between two hosts.
(11) UDP (User Datagram Protocol)
UDP is a connectionless and unreliable transport layer protocol that does not guarantee that packets will reach their destination; reliability is provided by the application layer. UDP has low overhead and is more suitable for use in low-end embedded fields compared to TCP.
(12) Ports: TCP and UDP use 16-bit port numbers to identify upper-layer users, i.e., application layer protocols; for example, the TCP port number for FTP service is 21, the TCP port number for Telnet service is 23, and the UDP port number for TFTP service is 69.
(1) CAN (Controller Area Network) bus is a multi-master serial communication bus, one of the most widely used field buses internationally, originally used for electronic control networks in automotive environments. An ideal single network constructed from a CAN bus can connect any number of nodes, though in practical applications, the number of nodes is limited by the electrical characteristics of the network hardware.
(2) The bus signal is transmitted using differential voltage. The two signal lines are called CAN_H and CAN_L, with static levels both at around 2.5V, indicating logic 1, also called
