Comprehensive Knowledge of Embedded System Hardware and Software Basics

This article mainly introduces the basic knowledge of embedded systems, covering all aspects of embedded software and hardware, hoping to be helpful to everyone.

1. Definition of Embedded Systems

(1) Definition: An application-centered, computer technology-based, software and hardware customizable, dedicated computer system that meets strict requirements for functionality, reliability, cost, size, and power consumption of application systems.

(2) Four stages of embedded system development: no operating system stage, simple operating system stage, real-time operating system stage, and Internet-oriented stage.

(3) Intellectual Property Core (IP Core): A functional module that has intellectual property rights, is specific in function, has standardized interfaces, and can be reused in multiple integrated circuit designs. It is a basic component for achieving System on Chip (SoC).

(4) IP core modules have three different levels of design: behavior, structure, and physical, corresponding to different descriptions of functional behavior, which can be divided into three categories: soft core, firm core, and hard core.

2. Components of Embedded Systems

Embedded systems consist of: hardware layer, intermediate layer, system software layer, and application software layer.

• Embedded core module = microprocessor + power circuit + clock circuit + memory

• Cache: Located between the main memory and the embedded microprocessor core, it stores the program codes and data that the microprocessor has used the most recently. Its main goal is to reduce the memory access bottleneck caused by the memory to the microprocessor core, making processing faster.

(1) Hardware Layer: Embedded microprocessor, memory, general device interface, and I/O interface.

(2) Intermediate Layer (also known as Hardware Abstraction Layer HAL or Board Support Package BSP). It separates the upper layer software from the underlying hardware, allowing upper layer software developers to develop based on the interfaces provided by the BSP layer without needing to care about the specifics of the underlying hardware.

• BSP has hardware relevance and operating system relevance. Designing a complete BSP requires completing two parts of work:

A. Hardware initialization of the embedded system and BSP functions.

• Chip-level initialization: A purely hardware initialization process that gradually sets the embedded microprocessor from the default state upon power-up to the working state required by the system.

• Board-level initialization: An initialization process that includes both hardware and software, establishing a running environment for subsequent system initialization and application programs.

• System-level initialization: A software-centric initialization process that initializes the operating system.

B. Design hardware-related device drivers.

(3) System Software Layer: Composed of RTOS, file system, GUI, network system, and general component modules. RTOS is the foundation and development platform for embedded application software.

(4) Application Software: Composed of application programs developed based on real-time systems.

3. Real-time Systems

(1) Definition: A system that can complete its functions and respond to external or internal events, synchronously or asynchronously, within specified or determined time.

(2) Distinction: General systems typically pursue average response time and user convenience; real-time systems focus mainly on system behavior in the worst-case scenario.

(3) Characteristics: Time constraints, predictability, reliability, and interaction with the external environment.

(4) Hard real-time (strong real-time): Refers to applications where time requirements must be fully met; otherwise, it may cause major safety accidents, significant loss of life and property, and ecological damage, such as aerospace and military applications.

(5) Soft real-time (weak real-time): Refers to applications that, while having time requirements, do not cause serious impact on system operation and environment if real-time tasks occasionally violate these requirements, such as monitoring systems and real-time information collection systems.

(6) Constraints of tasks include: time constraints, resource constraints, execution order constraints, and performance constraints.

4. Scheduling of Real-time Systems

(1) Scheduling: The entire process of determining when and where each task will be executed given a set of real-time tasks and system resources.

(2) Preemptive scheduling: Typically priority-driven scheduling, such as uCOS. Advantages include good real-time performance and fast response, with relatively simple scheduling algorithms that can guarantee time constraints for high-priority tasks; disadvantages include many context switches.

(3) Non-preemptive scheduling: Typically time-slice allocation scheduling, which does not allow tasks to be interrupted during execution. Once a task occupies the processor, it must complete execution or voluntarily relinquish control, such as WinCE. Advantages include fewer context switches; disadvantages include low effective resource utilization of the processor and poor schedulability.

(4) Static table-driven policy: The system generates a runtime schedule based on the time constraints and relationships of various tasks before running, indicating the starting execution time and duration of each task.

(5) Priority-driven policy: Determines the execution order of tasks based on their priority levels.

(6) Classification of real-time tasks: periodic tasks, sporadic tasks, and aperiodic tasks.

(7) General structural model of real-time systems: Data acquisition tasks implement the collection of sensor data, data processing tasks process the collected data and send the processed data to the actuator management tasks for execution.

5. Architecture of Embedded Microprocessors

(1) Von Neumann architecture: Programs and data share a single storage space, with program instruction storage addresses and data storage addresses pointing to different physical locations in the same memory, using a single address and data bus, with the same width for both programs and data. Examples include: 8086, ARM7, MIPS…

(2) Harvard architecture: Programs and data are two independent memories, each independently addressed and accessed, which separates program storage from data storage. Examples include: AVR, ARM9, ARM10…

(3) Comparison of features of CISC and RISC.

The time P required to execute a program can be calculated using the following formula: P=I×CPI×T, where:

• I: The number of instructions executed by the high-level language program when compiled and run on the machine.

• CPI: The average number of cycles required to execute each instruction.

• T: The time for each machine cycle.

(4) The idea of pipelining: In the CPU, the serial execution process of an instruction is transformed into overlapping execution of several instruction subprocesses in the CPU.

(5) Pipelining metrics:

• Throughput: The number of results processed by the pipeline in a unit time. If the subprocesses of the pipeline take different lengths of time, the throughput should be the inverse of the longest subprocess.

• Establishment time: The time from when the pipeline starts working to when it reaches maximum throughput. If m subprocesses take the same time, t, then establishment time T=mt.

(6) Byte order of information storage

• A. Memory unit: byte (8 bits)

• B. Word length determines the addressing capability of the microprocessor, that is, the size of the virtual address space.

• C. The virtual address space of a 32-bit microprocessor is 2^32, which is 4GB.

• D. Little-endian byte order: The low byte is at the low address in memory, and the high byte is at the high address in memory.

• E. Big-endian byte order: The high byte is at the low address in memory, and the low byte is at the high address in memory.

• F. The storage order of network devices depends on the data link layer in the OSI model.

6. Basics of Logic Circuits

(1) Logic circuits are classified into combinational logic circuits and sequential logic circuits based on whether they have storage functions.

(2) Combinational logic circuits: The output of the circuit at any moment depends only on the input signals at that moment and is independent of the state of the circuit before the input signals acted. Commonly used logic circuits include decoders and multiplexers.

(3) Sequential logic circuits: The output of the circuit at any moment depends not only on the input at that moment but also on the state of the circuit at that moment. Therefore, sequential circuits must include memory elements. Flip-flops are the basic components of sequential logic circuits. Commonly used sequential logic circuits include registers and counters.

(4) Truth tables, Boolean algebra, De Morgan’s laws, and concepts of gate circuits.

(5) NOR (negative OR) and NAND (negative AND) gate circuits are called universal gate circuits, which can implement any logical function.

(6) Decoder: A combinational logic network with multiple inputs and outputs. Each input of an n-bit binary code can have at most one valid output among m outputs. When m=2^n, it is a full decoder; when m<2^n, it is a partial decoder.

(7) Due to the low output current of integrated circuits at high levels and relatively larger output current at low levels, integrated gate circuits are often driven by low levels when directly driving LEDs. Liquid crystal seven-segment displays (LCD) utilize the different optical characteristics of liquid crystals under applied and non-applied electric fields to display characters.

(8) Clock signals are the basis of sequential logic, used to determine the appropriate state updates in logic units. Synchronization is the main constraint in clock-controlled systems.

(9) When selecting flip-flops, the triggering method is a crucial factor. There are two triggering methods:

Level-triggered: Simple structure, commonly used to form temporary storage.

Edge-triggered: Has strong resistance to data line interference, commonly used to form registers, counters, etc.

7. Bus Circuits and Signal Driving

(1) A bus is a collection of various signal lines, serving as a common pathway for transmitting data, addresses, and control information between components in an embedded system. At any given moment, each pathway line can transmit one binary signal. Depending on the type of information transmitted by the bus, it can be divided into: data bus (DB), address bus (AB), and control bus (CB).

(2) Main parameters of the bus:

• Bus bandwidth: The amount of data that can be transmitted on the bus within a certain time, usually expressed in MByte/s.

• Bus width: The number of bits (bit) that can be transmitted simultaneously on the bus, commonly referred to as the concept of bus width, such as 32-bit, 64-bit, etc. The wider the bus width, the greater the data transmission rate per second, that is, the wider the bus bandwidth.

• Bus frequency: The working clock frequency measured in MHz. The higher the operating frequency, the faster the bus speed, and the wider the bus bandwidth.

• Bus bandwidth = Bus width × Bus frequency / 8, measured in MBps.

• Common buses: ISA bus, PCI bus, IIC bus, SPI bus, PC104 bus, and CAN bus, etc.

(3) Only devices with tri-state outputs can be connected to the data bus, and the commonly used tri-state gate is the output buffer.

(4) When the load connected to the bus exceeds its load capacity, a buffer or driver must be added between the bus and the load, with the most common being the tri-state buffer, which serves to drive and isolate.

(5) The use of bus multiplexing technology can achieve the sharing of data and address buses. However, it brings two issues:

• A. Additional external circuits are needed to multiplex and decouple the bus signals, such as address latches.

• B. The bus speed is relatively lower than that of non-multiplexed bus systems.

(6) Two types of bus communication protocols: synchronous mode and asynchronous mode.

(7) The solution to the bus arbitration problem is based on the concept of priority (priority).

8. Level Conversion Circuits

(1) Digital integrated circuits can be divided into two major categories: bipolar integrated circuits (TTL) and metal-oxide-semiconductor (MOS).

(2) CMOS circuits are widely used due to their extremely low static power consumption, high operating speed, and strong anti-interference capability.

(3) The solution to the interface difficulties between TTL and CMOS circuits is to connect a pull-up resistor R between the TTL circuit output and the power supply. The value of the pull-up resistor R is determined by the high-level output leakage current IOH of TTL, and different series of TTL should use different R values.

9. Basics of Programmable Logic Devices

This content can be conceptually understood overall.

10. Basics of Information Representation and Computation in Embedded Systems

(1) Carry counting system and conversion: This is relatively simple and should also be mastered how to perform conversions, as it may be a potential exam question.

(2) Representation of numbers in computers: source code, one’s complement, and two’s complement.

• The one’s complement of a positive number is the same as its source code, while the one’s complement of a negative number is obtained by inverting the bits of its source code excluding the sign bit.

• The two’s complement of a positive number is the same as its source code, while the two’s complement of a negative number is obtained by adding one to its one’s complement.

• For example, the source code of -98 is: 11100010B

• One’s complement: 10011101B

• Two’s complement: 10011110B

(3) Fixed-point representation: The position of the decimal point is artificially fixed and does not change.

• Floating-point representation: The position of the decimal point is variable, consisting of a mantissa and an exponent.

• Any binary N can be expressed as: N=2^P×S, where S is the mantissa and P is the exponent.

(4) Chinese character representation, understanding the conversion between GB2318-80 China standard code and internal code.

(5) Parameters of waveform quantization in speech coding (there may be simple calculation questions).

• Sampling frequency: The number of samples taken in one second, reflecting the interval size between sampling points.

• The upper limit of human hearing is 20kHz, so a sampling frequency above 40kHz is sufficient for human satisfaction.

• The sampling frequency used in CDs is 44.1kHz.

• Measurement accuracy: The quantization level of the sample, with the currently standard sampling levels being 8-bit and 16-bit.

• Number of channels: mono and stereo. Stereo requires double the storage space.

11. Error Control Coding

(1) Based on the functionality of the code group, it can be divided into error detection codes and error correction codes. Error detection codes are codes that can automatically detect errors, such as parity check codes; error correction codes are codes that can not only detect errors but also automatically correct them, such as cyclic redundancy check codes.

(2) Parity check codes, Hamming codes, cyclic redundancy check codes (CRC).

12. Measurement Items of Embedded Systems

(1) Performance indicators: divided into component performance indicators and comprehensive performance indicators, mainly including: throughput, real-time performance, and various utilization rates.

(2) Reliability and safety

Reliability is the most important and prominent basic requirement of embedded systems, ensuring that an embedded system can operate normally, usually measured by Mean Time Between Failures (MTBF).

(3) Maintainability: Generally represented by Mean Time To Repair (MTTR).

(4) Availability

(5) Power consumption

(6) Environmental adaptability

(7) Universality

(8) Security

(9) Confidentiality

(10) Scalability

The price in the cost-performance ratio should include not only the direct purchase price of the embedded system but also installation costs, several years of operation and maintenance costs, and software rental fees.

13. Evaluation Methods for Embedded Systems: Measurement Method and Model Method

(1) The measurement method is the most direct and basic method, requiring resolution of two issues:

• A. Determine the system parameters to be measured based on the research objectives.

• B. Select measurement tools and methods.

(2) There are two measurement methods: sampling method and event tracking method.

(3) Model methods can be divided into analytical model methods and simulation model methods. Analytical model methods use mathematical equations to characterize the system model, while simulation model methods dynamically express the state of embedded systems through the operation of simulation programs for statistical analysis and performance metrics.

(4) The most commonly used analytical model is the queuing model, which includes three parts: input flow, queuing rules, and service institutions.

(5) Evaluating the system using models requires resolving three issues: designing models, solving models, and calibrating and validating models.

Interface Technology

1. Flash Memory

(1) Flash memory is a type of non-volatile memory that can be divided into NOR Flash and NAND Flash based on structural differences.

(2) Characteristics of Flash memory:

• A. Block structure: Physically divided into several blocks, which are independent of each other.

• B. Erase before write: Flash write operations can only change data bits from 1 to 0, not from 0 to 1, so before writing to the memory, an erase operation must be performed to initialize the pre-written data bits to 1. The minimum unit for the erase operation is a block, not a single byte.

• C. Operation instructions: To perform a write operation, it must input a series of special instructions (NOR Flash) or complete a sequence of timings (NAND Flash) to write data.

• D. Bit inversion: Due to the inherent characteristics of Flash, during read and write processes, occasionally one or several bits may produce data errors. Bit inversion cannot be avoided and can only be processed afterwards through other means.

• E. Bad blocks: Once a block is damaged, it cannot be repaired. Operations on damaged blocks yield unpredictable results.

(3) Characteristics of NOR Flash:

Application programs can run directly in Flash memory without needing to read the code into system RAM first. NOR Flash has high transmission efficiency, particularly in small capacities of 1MB to 4MB, providing high cost-effectiveness; however, its low write and erase speeds significantly affect its performance.

(4) Characteristics of NAND Flash:

Can achieve high storage density and has fast write and erase speeds, which is why all USB drives use NAND Flash as their storage medium. The challenge of using NAND Flash is that it requires a special system interface.

(5) Differences between NOR Flash and NAND Flash:

• A. NOR Flash has slightly faster read speeds than NAND Flash.

• B. NAND Flash has much faster erase and write speeds compared to NOR Flash.

• C. NAND Flash has poor random read capabilities and is suitable for large volume continuous reads.

• D. NOR Flash has an SRAM interface, providing sufficient address input for addressing and enabling easy access to each byte internally. NAND Flash shares an 8-bit bus for address, data, and commands (some products use 16 bits), requiring complex I/O interfaces to access data serially for each read and write operation.

• E. NOR Flash generally has smaller capacities, typically ranging from 1MB to 8MB; NAND Flash is only used in products over 8MB. Therefore, NOR Flash is used for code storage media, while NAND Flash is suitable for data storage.

• F. The maximum erase/write cycle for each block in NAND Flash is one million times, while for NOR Flash, it is one hundred thousand times.

• G. NOR Flash can be connected like other memory and can run code directly on it; NAND Flash requires a special I/O interface, and a driver program must be written before it can execute other operations. This means that designers must perform virtual mapping throughout the use of NAND Flash to avoid writing to bad blocks.

• H. NOR Flash is used in fields that require high data reliability for code storage, communication products, and network processing, known as code flash; NAND Flash is used in fields requiring high storage capacity, such as MP3 players, storage cards, USB drives, etc., known as data flash.

2. RAM Memory

(1) Characteristics of SRAM:

SRAM represents static random access memory, which retains a value as long as powered; it has no refresh cycle and is composed of flip-flops, resulting in low integration density, with each SRAM storage unit consisting of 6 transistors, making it more expensive. It has higher speed rates and is commonly used in high-speed buffer memory. Typically, SRAM has four pins:

• CE: Chip select signal, active low.

• R/W: Read/write control signal.

• ADDRESS: A set of address lines.

• DATA: A set of bidirectional signal lines for data transmission.

(2) Characteristics of DRAM:

DRAM represents dynamic random access memory. This type of semiconductor memory stores data in the form of electric charges. Each storage unit consists of a transistor and a capacitor, with data stored in the capacitor. The capacitor loses charge due to leakage, making DRAM devices unstable. It must be refreshed regularly to retain data.

DRAM has a more complex interface, typically having the following pins:

• CE: Chip select signal, active low.

• R/W: Read/write control signal.

• RAS: Row address strobe signal, usually connected to the high-order part of the address.

• CAS: Column address strobe signal, usually connected to the low-order part of the address.

• ADDRESS: A set of address lines.

• DATA: A set of bidirectional signal lines for data transmission.

(3) Characteristics of SDRAM:

SDRAM represents synchronous dynamic random access memory. Synchronous means that the memory works based on a synchronous clock, with internal command transmission and data transfer based on it; dynamic means that the memory array needs constant refreshing to prevent data loss. It usually works at a main frequency of 133MHz.

(4) Characteristics of DDRAM:

DDRAM represents double data rate synchronous dynamic random access memory, also known as DDR. DDRAM is based on SDRAM technology, where SDRAM transmits data once per clock cycle, while DDR memory transmits data twice per clock cycle, once on the rising edge and once on the falling edge of the clock. At a main frequency of 133MHz, DDR memory bandwidth can reach 133×64b/8×2=2.1GB/s.

3. Hard Disk, Optical Disk, CF Card, SD Card

4. GPIO Principles and Structures

GPIO is the most basic form of I/O, consisting of a set of input or output pins. Some GPIO pins can be programmed to change their working direction, typically having two control registers: data register and data direction register. The data direction register sets the port’s direction. If the pin is set to output, the data register controls the state of that pin. If the pin is set to input, the state of this input pin is controlled by the logic circuit layer on the pin.

5. A/D Interface

(1) An A/D converter is a circuit that converts analog electrical quantities into digital quantities. There are many methods to achieve A/D conversion, commonly used methods include counting method, dual integration method, and successive approximation method.

(2) Counting A/D conversion method

The main components of its circuit include: comparator, counter, D/A converter, and standard voltage source.

The working principle is simple: there is a counter that starts counting from 0, incrementing by 1 each time, with the value being input to the D/A converter, which produces a comparison voltage VO to compare with the input analog voltage VIN. If VO is less than VIN, the counter continues to increment until VO is greater than VIN; at this point, the accumulated value of the counter is the output value of the A/D converter.

This conversion method is simple but relatively slow, especially for higher analog voltages, where the conversion speed is even slower. For example, for an 8-bit A/D converter, if the input analog quantity is at its maximum value, the counter must count from 0 to 255, performing 255 D/A conversions and voltage comparisons to complete the conversion.

(3) Dual integration A/D conversion method

The main components of its circuit include: integrator, comparator, counter, and standard voltage source.

The working principle is that the circuit first integrates the input voltage to be measured for a fixed time, then reversely integrates with a standard voltage at a fixed slope until it returns to the starting value. Due to the use of a fixed slope, the time for reverse integration to return to the starting value is proportional to the input analog voltage value; the larger the input analog voltage, the longer it takes to return. By using a standard high-frequency clock pulse to measure the time taken for reverse integration, the corresponding digital quantity for the input analog voltage can be obtained, completing the A/D conversion.

This method has strong resistance to industrial frequency interference and high conversion accuracy but is generally used for low-frequency conversions, typically below 10Hz, mainly used in digital testing instruments, temperature measurements, etc.

(4) Successive approximation A/D conversion method

The main components of its circuit include: comparator, D/A converter, successive approximation register, and reference voltage source.

The working principle is essentially a binary search method, similar to using a balance scale. During A/D conversion, the D/A converter increases the conversion bit from high to low, generating different output voltages, comparing the input voltage with the output voltage. First, the highest bit is set to 1, which is equivalent to comparing half of the reference voltage with the input voltage; if the input voltage is less than half of the reference voltage, the highest bit is set to 0, otherwise set to 1. Then the next highest bit is set to 1, performing a binary search within the half range, and so on, approaching the value step by step.

This method is fast and has high conversion accuracy, requiring only M clock pulses to complete for an N-bit A/D converter, making it widely used for measuring changes in transient processes of tens to hundreds of microseconds.

(5) Important indicators of A/D conversion (there may be simple calculation questions)

• A. Resolution: Reflects the A/D converter’s ability to respond to small changes in input, usually expressed as the voltage level corresponding to the least significant bit (LSB) of the digital output. An n-bit A/D converter can reflect 1/2^n of the full-scale analog input voltage.

• B. Range: The range of analog input voltages that can be converted, divided into unipolar and bipolar types.

• C. Conversion time: The time required to complete one A/D conversion, with its reciprocal representing the conversion rate.

• D. Accuracy: Accuracy and resolution are two different concepts; even with high resolution, accuracy may not be high due to temperature drift, linearity, etc. Accuracy can be expressed in absolute and relative terms. Absolute accuracy is expressed as the fractional value of the least significant bit (LSB) of the digital quantity, while relative accuracy is expressed as a percentage of the full-scale analog voltage.

• For example, for a full-scale of 10V, a 10-bit A/D chip with an absolute accuracy of ±1/2 LSB means the minimum effective unit of LSB is: 10/1024=9.77mV, with absolute accuracy of 9.77mV/2=4.88mV and relative accuracy of: 0.048%.

6. Basic D/A Interface

(1) D/A converters convert digital quantities into analog quantities.

(2) In integrated circuits, a T-type network is usually used to convert digital quantities into analog currents, which are then converted into analog voltages by operational amplifiers. D/A conversion essentially requires these two steps.

(3) Classification of D/A converters:

• A. Voltage output type: commonly used as high-speed D/A converters.

• B. Current output type: typically used with external operational amplifiers.

• C. Multiplicative type: can be used as modulators and to digitally attenuate input signals.

(4) Main indicators of D/A converters: resolution, establishment time, linearity, conversion accuracy, temperature coefficient.

7. Keyboard Interface

(1) Two forms of keyboards: linear keyboards and matrix keyboards.

(2) There are two common methods for recognizing closed keys on a keyboard: row scanning method and row inversion method.

(3) The row scanning method is the commonly used method for recognizing keys on matrix keyboards, which is performed in two steps:

• A. Identify which column key is pressed: set all row lines to low, check if any column line is low; if any column line is low, it indicates that a key in that column is pressed, otherwise, no key is pressed.

• B. If a key is pressed in a column, identify which row is pressed: set one row to low while keeping the others high, check for changes in the column; if the column level changes to low, it indicates that the key at the intersection of that row and column is pressed.

8. Display Interface

(1) The basic principle of LCD is to control the passage of light through different liquid crystal units by supplying power.

(2) There are two ways to provide light sources for LCD: projection type and reflection type. The LCD display of laptops is projection type, where there is a light source behind the screen, so external light sources are not needed. Generally, the LCDs used on microcontrollers are reflection type, requiring external light sources to work. Electroluminescent (EL) is a method of providing light sources for LCD screens.

(3) Based on the driving method, common LCDs can be classified into three types: Twisted Nematic (TN), Super Twisted Nematic (STN), and Thin Film Transistor (TFT).

(4) There are two types of LCDs available in the market: LCD display modules with driving circuits, which can be driven simply by bus; and LCD displays without driving circuits, which use controller scanning methods.

(5) Typically, when the LCD controller works, it requests the bus through DMA, directly reading the data from the specified address (display buffer) in SDRAM, which is then converted into the scanning data format for the LCD by the LCD controller to drive the LCD display directly.

(6) The VGA interface is essentially an analog interface, commonly using a unified 15-pin connector, including 2 NC signals, 3 display data lines, 5 GND signals, 3 RGB color components, 1 horizontal sync signal, and 1 vertical sync signal. The voltage levels for the color components are based on the RS343 standard defined by EIA.

9. Touch Screen Interface

(1) Based on the working principle, touch screens can be divided into: surface acoustic wave screens, capacitive screens, resistive screens, and infrared screens.

(2) The control of touch screens uses specialized chips, such as ADS7843.

10. Audio Interface

(1) Basic principle: The data input from the microphone is decoded by the audio codec to complete A/D conversion, and the decoded audio data is sent to the DSP or CPU for processing via the audio controller, after which the data is sent to the audio encoder for D/A conversion and output through the speaker.

(2) There are various formats for digital audio, with the three most common being:

• A. Digital audio (PCM): The data format used by CDs or DVDs, with a sampling frequency of 44.1kHz. At 16-bit precision, the PCM audio data rate is 1.41Mb/s; at 32-bit precision, it is 2.42Mb/s. A 700MB CD can store about 60 minutes of music in 16-bit PCM data format.

• B. MPEG Layer 3 audio (MP3): The audio format used by MP3 players, with stereo MP3 data rates ranging from 112kb/s to 128kb/s.

• C. ATSC digital audio compression standard (AC3): The digital audio encoding standard for digital TV, HDTV, and movies, with stereo AC3 encoded data rates of 192kb/s.

(3) IIS is a commonly used serial audio digital interface for encoding or decoding audio data. The IIS bus only handles audio data, while other control signals need to be transmitted separately. IIS uses three serial buses: data line SD, field selection line WS, and clock signal line SCK.

(4) When the data width of the sender and receiver differs, the sender does not consider the receiver’s data width. If the sender’s data width is smaller than the system field width, it pads with zeros at the low end; if the sender’s data width exceeds the receiver’s width, the excess bits beyond LSB are truncated. The field selection WS is used to select the left or right channel; WS=0 indicates the left channel is selected, while WS=1 indicates the right channel. Additionally, WS allows the receiving device to store the previous byte and prepare to receive the next byte.

11. Serial Interface

(1) Serial communication means transmitting data bit by bit. Compared to parallel communication, serial communication has fewer transmission lines and lower costs, making it particularly suitable for long-distance transmission; however, it is slower.

(2) There are three basic communication modes for serial data transmission: simplex, half-duplex, and full-duplex.

(3) In terms of information format, serial communication can be divided into two types: synchronous communication and asynchronous communication.

• A. Asynchronous transmission: Each character is treated as independent information for transmission, following a fixed and predetermined timing, but the timing between characters is arbitrary. In asynchronous communication, characters are transmitted in frames, with each frame being synchronized by a start bit. The time interval between each character in a frame is fixed, while the time interval between two adjacent frames is not fixed.

• B. Synchronous transmission: In synchronous mode, not only are characters synchronized between each other, but the timing between characters is also synchronized, meaning that multiple characters are grouped into a block, with 1-2 synchronization characters added before each block of information, followed by appropriate error detection data before transmission.

(4) Asynchronous communication must adhere to three regulations:

• A. Character format: Start bit + data + parity bit + stop bit (parity bit can be omitted), with the low bit transmitted first.

• B. Baud rate: The number of bits transmitted per second.

• C. Parity bit: Odd/even parity.

• a. Odd parity: A parity bit is added to ensure an odd number of “1” bits in the character.

• b. Even parity: A parity bit is added to ensure an even number of “1” bits in the character.

(5) The electrical characteristics of RS-232C: negative logic.

• A. On TxD and RxD: Logic 1 is -3V to -15V, logic 0 is 3V to 15V.

• B. On control lines such as TES, CTS, DTR, DCD, etc.:

• Effective signal (ON state) is 3V to 15V

• Inactive signal (OFF state) is -3V to -15V

(6) The level conversion between TTL standards and RS-232C standards is achieved using integrated chip RS232.

(7) RS-422 serial communication interface

• A. RS-422 is a unidirectional, balanced transmission specification for single machine sending and multi-machine receiving, with a transmission rate of up to 10Mb/s.

• B. RS-422 uses differential transmission, also known as balanced transmission, using a pair of twisted wires.

• C. RS-422 requires a termination resistor, with its resistance value approximately equal to the characteristic impedance of the transmission cable.

(8) RS-485 serial bus interface

• A. RS-485 is a standard built on RS-422, adding multi-point, two-way communication capabilities, with communication distances ranging from several meters to several kilometers.

• B. RS-485 transceivers use balanced transmission and differential reception, providing the ability to suppress common-mode interference.

• C. RS-485 requires two termination resistors. For short-distance transmission (less than 300m), termination resistors may not be needed.

12. Parallel Interface

(1) The data transmission rate of parallel interfaces is eight times faster than that of serial interfaces, with a standard parallel interface data transmission rate of 1Mb/s, commonly used for connecting printers, scanners, etc., and is also known as the printer port.

(2) Parallel interfaces can be divided into SPP (Standard Parallel Port), EPP (Enhanced Parallel Port), and ECP (Extended Parallel Port).

(3) Parallel buses are classified into standard and non-standard types. Commonly used standard parallel buses include IEEE 488 and ANSI SCSI buses. The MXI bus is a high-performance non-standard general-purpose multi-user parallel bus.

13. PCI Interface

(1) The PCI bus is a high-performance 32-bit and 64-bit bus for multiplexing addresses and data, serving as an interconnection mechanism between microprocessors and peripheral control components and peripheral add-on boards.

(2) In terms of data width, PCI defines a 32-bit data bus that can be expanded to 64 bits. In terms of bus speed, there are two types: 33MHz and 66MHz.

(3) Compared to the ISA bus, the PCI bus multiplexes address and data buses, supporting plug-and-play and interrupt sharing functions.

14. USB Interface

(1) The main features of the USB bus:

• A. Simple to use, plug-and-play.

• B. Each USB system has a host, and up to 127 devices can be connected in this USB network.

• C. Wide application range, supporting multiple devices to operate simultaneously.

• D. Low-cost cables and connectors using a unified 4-pin plug.

• E. Strong error correction capability.

• F. Low protocol overhead results in high bus performance, suitable for the development of low-cost peripherals.

• G. Supports multi-data flow and multi-message flow transmission between host and devices, as well as synchronous and asynchronous transmission types.

• H. Bus-powered, capable of providing 5V/100mA to devices.

(2) The USB system is described by three parts: USB host, USB device, and USB interconnection.

(3) The data transmission rates supported by the USB bus include three types: high-speed signaling rate of 480Mb/s; full-speed signaling rate of 12Mb/s; low-speed signaling rate of 1.5Mb/s.

(4) The USB bus cable consists of four wires: a pair of twisted signal wires and a pair of power wires.

(5) USB is a polling bus, with the master controller initiating all data transmissions. The peripherals connected to USB share the USB bandwidth through a token-based protocol scheduled by the host.

(6) Most bus transactions involve the transmission of three packets:

• A. Token packet: Indicates what transaction is to be performed on the bus, the USB device to be addressed, and the direction of data transfer.

• B. Data packet: Transmits data or indicates that there is no data to transmit.

• C. Handshake packet: Indicates whether the transmission was successful.

(7) The USB data transmission model between the host and the device endpoints is called a pipe. There are two types of pipes: stream and message. Message data has a structure defined by USB, while data streams do not.

(8) The transaction scheduling table allows for traffic control over certain stream pipes, adjusting the data transmission rate at the hardware level by using the NAK (negative acknowledgment) handshake signal to prevent buffer overflow or underflow.

(9) The most notable feature of USB devices is plug-and-play.

(10) Working principle: When a USB device is plugged into a USB endpoint, the host communicates with the device’s endpoint 0 through the default address 0. In this process, the host issues a series of standard requests to obtain the descriptor, through which it acquires all the device information of interest, thereby understanding the device’s status and how to communicate with it. Subsequently, the host issues a Set Address request to assign a unique address to the device. After this, the host communicates with the device using the assigned address and no longer uses the default address 0.

15. SPI Interface

(1) SPI is a synchronous protocol interface, with all transmissions referring to a common clock generated by the host, and the receiving external device uses this clock to synchronize the reception of serial bit streams.

(2) When multiple devices are connected to the same SPI interface, the host selects the desired slave device using the slave select pin of the device.

(3) SPI mainly uses four signals: Master Output/Slave Input (MOSI), Master Input/Slave Output (MISO), Serial Clock (SCLK), and Chip Select (CS).

(4) Both the host and the slave include a serial shift register, and the host initiates a data transmission by writing a byte to its SPI serial register. The register transmits the byte to the slave via the MOSI signal line, and the slave returns the contents of its shift register back to the host via the MISO signal line, thus exchanging the contents of the two shift registers.

(5) Write and read operations of the slave are synchronized, making SPI a very efficient protocol.

(6) If only a write operation is performed, the host simply ignores the received byte; conversely, if the host wants to read a byte from the slave, it must send an empty byte to prompt the slave’s transmission.

16. IIC Interface

(1) The IIC bus is a high-performance multi-master bus with bus arbitration and synchronization for high and low-speed devices.

(2) The IIC bus requires two lines: Serial Data Line (SDA) and Serial Clock Line (SCL).

(3) Each device on the bus has a unique address for identification, and each device can act as either a transmitter or receiver (depending on the device’s function).

(4) The IIC bus has four operational modes: master send, master receive, slave send, and slave receive.

(5) There are three types of signals during data transmission on IIC:

• A. Start signal: When SCL is low, SDA transitions from high to low.

• B. Stop signal: When SCL is low, SDA transitions from low to high.

• C. Acknowledge signal: The receiver sends a specific low level to the sender after receiving 8 bits of data in the ninth pulse.

(6) After the master device sends a start signal, it immediately sends a slave address to notify the slave device with which it will communicate. One byte of address includes 7 bits of address information and one bit indicating the direction of transmission; if the 7th bit is 0, it indicates a write operation, and if it is 1, it indicates a read operation.

(7) Each byte transmitted on the SDA line is 8 bits long, and there is no limit on the number of bytes transmitted in each transmission. The first byte after the start signal is the address field, and each transmitted byte is followed by an acknowledgment bit (ACK), with the most significant bit (MSB) of the serial data transmitted first.

(8) If the data receiver can no longer receive more data, it can interrupt the transmission by keeping SCL low, forcing the data sender to wait until SCL is released. This allows synchronization between high and low-speed devices.

(9) The working process of the IIC bus: SDA and SCL are both bidirectional. When idle, both SDA and SCL are high, and only when SDA goes low, followed by SCL going low, does data transmission on the IIC bus begin. Each bit transmitted on the SDA line is sampled on the rising edge of SCL, and the bit must remain valid until SCL goes low again, at which point the next bit is transmitted before SCL returns to high, and then SDA also goes high, indicating the end of data transmission.

17. Ethernet Interface

(1) The most commonly used Ethernet protocol is the IEEE802.3 standard.

(2) Transmission encoding: Manchester encoding and differential Manchester encoding.

• A. Manchester encoding: Each bit has a level transition in the middle, with a transition from high to low indicating “0” and from low to high indicating “1.”

• B. Differential Manchester encoding: Each bit has a level transition in the middle, using the presence or absence of a transition at the start of each code element to indicate “0” or “1,” with a transition indicating “0” and no transition indicating “1.”

(3) Compared to each other, Manchester encoding is simpler, while differential Manchester encoding provides better noise suppression performance.

(4) Characteristics of Ethernet data transmission:

• A. All data bits are transmitted starting from the low bit, using Manchester encoding for the bit stream.

• B. Ethernet is a bus multiplexing method based on collision detection, automatically performed by hardware.

• C. The length of transmitted data includes destination address DA + source address SA + type field TYPE + data segment DATA + padding bit PAD, with a minimum of 60B and a maximum of 1514B.

• D. Typically, Ethernet cards can receive data addressed to three types of addresses: broadcast address, multicast address, and their own address.

• E. Each two network cards have different physical addresses, which are unique in the world, assigned by a specialized organization.

(5) There are two methods for implementing embedded Ethernet interfaces:

• A. Embedded processor + network card chip (e.g., RTL8019AS, CS8900, etc.)

• B. Processors with Ethernet interfaces.

(6) TCP/IP is a layered protocol consisting of: physical layer, data link layer, network layer, transport layer, and application layer. Each layer implements a specific function, corresponding to one or several transmission protocols, with each layer functioning as an independent data packet relative to its lower layer. The protocols at each layer are as follows:

• A. Application layer: BSD socket.

• B. Transport layer: TCP, UDP.

• C. Network layer: IP, ARP, ICMP, IGMP.

• D. Data link layer: IEEE802.3 Ethernet MAC.

• E. Physical layer: Binary bit stream.

(7) ARP (Address Resolution Protocol)

• A. The network layer uses a 32-bit address to identify different hosts (i.e., IP address), while the link layer uses a 48-bit physical address (MAC) to identify different Ethernet or token ring interfaces.

• B. Function of ARP: To achieve the conversion from IP address to the corresponding physical address.

(8) ICMP (Internet Control Message Protocol)

• A. It is used at the IP layer to exchange error messages and other important control information with other hosts or routers.

• B. ICMP messages are transmitted within IP packets.

• C. The network diagnostic tools ping and traceroute are actually based on the ICMP protocol.

(9) IP (Internet Protocol)

• A. IP operates at the network layer and is the core protocol in the TCP/IP protocol family.

• B. All TCP, UDP, ICMP, and IGMP data are transmitted in the format of IP packets.

• C. TTL (Time to Live field): Specifies the lifetime of an IP packet (the number of routers it can pass through).

• D. IP provides unreliable, connectionless data packet delivery service, which is efficient and flexible.

(10) TCP (Transmission Control Protocol)

TCP is a connection-oriented, reliable transport layer protocol that provides high reliability end-to-end data communication between two hosts.

(11) UDP (User Datagram Protocol)

UDP is a connectionless, unreliable transport layer protocol that does not guarantee that data packets will reach their destination; reliability is provided by the application layer. UDP has low overhead and is more suitable for low-end embedded fields compared to TCP.

(12) Port: TCP and UDP use 16-bit port numbers to identify upper-layer users, i.e., application layer protocols, such as TCP port number 21 for FTP service, TCP port number 23 for Telnet service, and UDP port number 69 for TFTP service.

18. CAN Bus Interface

(1) CAN (Controller Area Network) bus is a multi-master serial communication bus, one of the most widely used field buses internationally, initially used in electronic control networks in automotive environments. In an ideal single network constructed by a CAN bus, any number of nodes can be connected, although in practical applications, the data of the nodes is limited by the electrical characteristics of the network hardware.

(2) Bus signals are transmitted using differential voltages. Two signal lines are called CAN_H and CAN_L, with static values around 2.5V, indicating logic 1, also called “dominant.” Logic 0 is indicated by CAN_H being higher than CAN_L, usually with voltage values of CAN_H=3.5V and CAN_L=1.5V.

(3) When both “dominant” and “recessive” bits are sent simultaneously, the final bus value will be “dominant,” which establishes the basis for CAN bus arbitration.

(4) A single bit time on the CAN bus can be divided into four parts: synchronization segment, propagation time segment, phase buffer segment 1, and phase buffer segment 2.

(5) There are two formats for CAN bus data frames: standard format and extended format, including: frame start, arbitration field, control field, data field, CRC field, ACK field, and frame end.

(6) The hardware interface of the CAN bus includes: CAN bus controller and CAN transceiver. The CAN controller mainly performs tasks such as timing logic conversion, e.g., Philips’s SJA1000. The CAN transceiver is the physical layer chip of the CAN bus, realizing the conversion from TTL level to CAN bus electrical characteristics, e.g., TJA1050.

19. xDSL Interface

(1) xDSL (Digital Subscriber Line) technology involves connecting dedicated DSL modems on both sides of the existing user telephone line, utilizing the higher frequency bandwidth characteristics of digital signals for direct transmission, bypassing the intermediate A/D conversion, breaking through the limits of analog signal transmission at 56KB/s.

(2) DSL technology is mainly divided into symmetric and asymmetric types.

(3) Symmetric xDSL is more suitable for point-to-point connections in enterprises, such as file transfers, video conferencing, etc., where the amount of data sent and received is roughly the same.

(4) ADSL is a recently developed broadband access technology that uses twisted copper pairs to provide asymmetric broadband information services in both directions.

(5) ADSL transmits one high-speed downstream data, one lower-speed upstream data, and one analog telephone signal simultaneously over a pair of telephone lines. The signals are multiplexed using frequency division, occupying different frequency bands, with low frequencies transmitting voice; the middle narrow frequency band transmitting upstream channel data and control information; the remaining high frequency band transmitting downstream channel data, images, or high-speed data.

20. WLAN Interface

(1) WLAN (Wireless Local Area Network) is a product of combining computer networks and wireless communication technology to establish a local area network within a certain range, providing the functions of wired local area networks using wireless multi-access channels as the transmission medium.

(2) WLAN standards mainly target the physical layer and medium access control layer (MAC layer), covering all used wireless frequency ranges, control interface communication protocols, and other technical specifications and standards.

• A. IEEE 802.11: Defines the physical layer and MAC layer specifications, operating in the 2.4-2.4835GHz frequency band, with a maximum speed of 2Mb/s, which is the initial wireless local area network standard established by IEEE.

• B. IEEE 802.11b: Operates in the 2.4-2.4835GHz frequency band, with a maximum speed of 11Mb/s and a transmission distance of 50-150 inches. It operates in both point-to-point mode and basic mode, with the data transmission rate automatically switching between 11Mb/s, 5.5Mb/s, 2Mb/s, and 1Mb/s based on actual conditions.

• C. IEEE 802.11a: Operates in the 5.15-8.825GHz frequency band, with a maximum speed of 54Mb/s/72Mb/s and a transmission distance of 10-100m.

• D. IEEE 802.11g: A hybrid standard that has the transmission speed of IEEE 802.11a and better security than IEEE 802.11b, using two modulation methods to be compatible with both IEEE 802.11a and IEEE 802.11b.

(3) WLAN can be classified into two types of networks: peer-to-peer networks and infrastructure networks.

21. Bluetooth Interface

(1) The purpose of Bluetooth technology is to enable seamless resource sharing between specific mobile phones, portable computers, and various handheld communication devices within close proximity.

(2) The essence of Bluetooth technology is to establish a universal wireless air interface and its control software open standards. It operates in the globally common 2.4GHz ISM (Industrial, Scientific, Medical) frequency band, with a data transmission rate of 1Mb/s, using a time-division duplex scheme to achieve full-duplex transmission, with an ideal connection range of 10cm to 10m.

(3) The Bluetooth baseband protocol combines circuit-switched and packet-switched approaches.

(4) Characteristics of Bluetooth technology:

• A. Short transmission distance, typically within 10m.

• B. Uses frequency-hopping spread spectrum technology.

• C. Employs time-division multiplexing access technology to effectively avoid issues such as “collisions” and “hidden terminal.”

• D. Network technology.

• E. Language support.

• F. Error correction technology, using the FEC (Forward Error Correction) scheme.

(5) The Bluetooth interface is composed of three major units: wireless unit, baseband unit, and link management and control unit.

22. 1394 Interface

(1) As a standard bus, 1394 can bridge communication between different industrial devices, with up to 63 devices connected on a single bus.

(2) Characteristics of IEEE 1394:

• A. Supports multiple bus speeds to meet different application requirements.

• B. Plug-and-play support, hot-swappable.

• C. Supports both synchronous and asynchronous transmission methods.

• D. Supports point-to-point communication mode; IEEE 1394 is a multi-master bus.

• E. Complies with ANSI IEEE 1212 control and status register (CSR) standard, defining a 64-bit address space, capable of addressing 1024 buses with up to 63 nodes, each node capable of containing 256TB of memory space.

• F. Supports long-distance transmission.

• G. Supports fair arbitration principles, ensuring sufficient bandwidth for each transmission method.

• H. Six-wire cables include power lines, capable of transmitting 8-40V DC voltage.

(3) The protocol stack of IEEE 1394 consists of three layers: physical layer, link layer, and transaction layer, with an additional management layer. The physical and link layers are hardware-based, while the transaction layer is mainly software-based.

• A. The physical layer provides electrical and mechanical interfaces for IEEE 1394, with the function of reassembling byte streams and sending them to the destination node.

• B. The link layer provides data services to the transaction layer, including addressing, data framing, and data verification.

• C. The transaction layer provides services to applications.

• D. The management layer defines all protocols, services, and processes used by a management node.

23. Power Interface

(1) DC-DC converters have three types:

• A. Linear voltage regulators: Produce a voltage lower than the input voltage.

• B. Switching regulators: Can increase, decrease, or invert the input voltage.

• C. Charge pumps: Can increase, decrease, or invert the input voltage, but have limited current driving capability.

(2) The conversion process of any transformer does not have 100% efficiency, and regulators also consume current (static current), which comes from the input current. The larger the static current, the greater the power consumption of the regulator.

(3) Linear voltage regulators use decoupling capacitors at the input and output to filter, which helps stabilize the voltage and remove transient short-term pulse waveform interference in the power supply.

(4) The square relationship between voltage and power consumption means that the most efficient method is to execute code at lower clock rates with lower voltage requirements, rather than executing code at the highest clock rate first and then switching to idle sleep.

(5) The power supply is usually considered the “heart” of the entire system, with 50%-80% of the energy-saving potential of most electronic devices lying in the power supply system, and developing new types of switching power supplies is one of the main measures for energy saving.

(6) Design techniques for reducing power consumption:

• A. Use low-power devices, such as selecting CMOS circuit chips.

• B. Use highly integrated dedicated devices, and external device selection should also support low-power design as much as possible.

• C. Dynamically adjust the clock frequency and voltage of the processor, using low-frequency devices as much as possible when conditions allow.

• D. Utilize “power-saving” operating modes.

• E. Properly handle the idle pins of devices:

1. a. The power consumption of most digital circuit output terminals is much greater when outputting low levels than when outputting high levels; design should control the output time of low levels and keep them at high levels when idle.

2. b. Excess non-gate and non-inverting gate input terminals should be connected to low levels, while excess AND and OR gate input terminals should be connected to high levels.

3. c. For ROM or RAM and other devices with chip select signals, do not connect the “chip select” pin directly to ground to avoid keeping the device permanently activated; instead, it should be combined with the “read/write” signal, only enabling it during read/write operations.

• F. Implement power management, designing external device power control circuits to manage the power supply of “high power consumption” devices.

END