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🚀 Quick Overview of DISCO’s Ultra-Thin Wafer Processing Technology for “3D Stacked Chips” in 3 Minutes!

As semiconductor chips continue to evolve towards higher performance and miniaturization, 3D stacking technology has gradually become a hot topic in the semiconductor manufacturing industry. Among them, Through Silicon Via (TSV) technology has gained significant attention for its ability to significantly enhance chip performance and integration.

One of the key factors in achieving this technology is ultra-thinning technology. Recently, DISCO has conducted in-depth research on ultra-thin wafer processing, and today we will quickly explore the advantages of DISCO’s technology and its impact on chip characteristics!

📌 Why Adopt 3D Stacking Technology?

Traditionally, the performance enhancement of semiconductor chips relies on the miniaturization of two-dimensional planes, but this miniaturization is gradually approaching physical limits. 3D stacking technology offers a new solution:

✅By stacking multiple chip layers in the vertical direction, achieving higher integration and smaller footprint.

✅Connecting each chip layer through TSVs, shortening the length of connection lines, reducing parasitic resistance and capacitance, thereby decreasing signal delay and power consumption.

However, to achieve efficient 3D stacking, wafers must be ultra-thinned (even below 10 µm), making ultra-thinning technology crucial.

🔍 Detailed Explanation of Ultra-Thin Wafer Processing Technology

The ultra-thinning process mainly includes the following two steps:

1. Back Grinding (BG)

   Coarse grinding (#320): Quickly removes a large amount of silicon material to approach the target thickness.

   Fine grinding (#2000): Further thins the wafer and reduces surface damage.

2. Stress Relief Treatment

   Ultra Poligrind (UPG): An extremely fine dry grinding technology.

   Chemical Mechanical Polishing (CMP): A process that removes residual damage layers on the wafer surface through chemical and mechanical actions.

Through this process, the residual stress and damage layers on the wafer surface are significantly reduced, enhancing the mechanical strength and electrical reliability of the wafer.

📊 Experimental Results of DISCO’s Ultra-Thin Wafer Technology

DISCO has conducted ultra-thinning experiments on various wafers, including FRAM (Ferroelectric Random Access Memory), HP Logic (High-Performance Logic Chips), and DRAM (Dynamic Random Access Memory):

✅FRAM: Thinned to 9 µm.

✅HP Logic: Thinned to 7 µm.

✅DRAM: Thinned to 4 µm.

Experimental analysis shows:

The thickness uniformity (TTV) of the ultra-thin wafers is controlled within 2 µm, and when the DRAM wafer is thinned to 4 µm, the TTV even reaches 1.02 µm, demonstrating extremely high processing precision.

After thinning FRAM to 9 µm, the ferroelectric characteristics were not significantly damaged.

After thinning HP Logic to 7 µm, the current driving characteristics of the transistors remained stable.

When DRAM is thinned to 4 µm, the retention characteristics of the memory did not show significant degradation.

The above results prove that DISCO’s ultra-thinning technology has no significant negative impact on the electrical performance of chips.

⚙️ Summary of Advantages of Ultra-Thin Wafer Processing

Ultra-thin wafers bring several key advantages:

Low Aspect Ratio TSV: Ultra-thin wafers can form low aspect ratio TSVs, reducing wiring resistance and parasitic capacitance, thereby enhancing chip performance.

Low Power Consumption: Shorter wiring lengths reduce overall chip power consumption.

Smaller Package Size: Suitable for mobile devices and high-density packaging needs.

Higher Mechanical Reliability: Stress relief technology effectively removes residual stress after wafer processing, enhancing chip strength.

📚 Glossary of Technical Terms

🔹 Through Silicon Via (TSV)

A conductive via that vertically passes through the silicon wafer, used to connect the chip layers in 3D stacked chips.

🔹 Back Grinding (BG)

A mechanical processing technique in semiconductor manufacturing that thins the wafer from the back side.

🔹 Stress Relief

A process that eliminates surface residual stress generated during processing through fine grinding or polishing, enhancing chip reliability.

🔹 TTV (Total Thickness Variation)

The maximum difference in wafer thickness; a smaller TTV value indicates more uniform thickness and higher processing quality.

🔹 FRAM (Ferroelectric RAM)

A memory chip that utilizes ferroelectric materials to achieve non-volatile storage.

🔹 Retention

The ability of a capacitor in a DRAM memory cell to hold charge, affecting the reliability of data storage.

Through DISCO’s research, we have learned about the significant advantages of ultra-thin wafer processing (≤10 µm) in 3D stacked chip technology:

✅The successful implementation of ultra-thin wafer processing can significantly enhance chip performance and reduce power consumption.

✅It has been proven to have no negative impact on the electrical characteristics of FRAM, HP Logic, and DRAM chips.

✅Future scalability to other semiconductor materials such as SiC and GaN will further promote the development of advanced chip packaging and manufacturing.

✅References:

https://www.disco.co.jp/jp/solution/technical_review/doc/TR16-06_%E4%B8%89%E6%AC%A1%E5%85%83%E7%A9%8D%E5%B1%A4%E3%83%87%E3%83%90%E3%82%A4%E3%82%B9%E5%90%91%E3%81%91%E3%81%AE%E3%82%A6%E3%82%A7%E3%83%BC%E3%83%8F%E6%A5%B5%E8%96%84%E5%8A%A0%E5%B7%A5%E3%81%A8%E3%83%87%E3%83%90%E3%82%A4%E3%82%B9%E7%89%B9%E6%80%A7%E3%81%B8%E3%81%AE%E5%BD%B1%E9%9F%BF_20160331.pdf

✅Reference Material Translation:

Silicon Wafer Ultra-Thinning Technology for 3D Stacked Chips and Its Impact on Chip Characteristics

(DISCO Technical Review, Mar. 2016)

Abstract

In the semiconductor industry, the adoption of Through Silicon Via (TSV) 3D stacking technology has received widespread attention to enhance chip performance and integration. Due to the demand for vertically stacked chips, thinning silicon wafers has become a necessary process. The ultra-thin wafer structure can form low aspect ratio TSVs, bringing various advantages such as reduced signal delay, lower power consumption, reduced TSV residual stress, and decreased process difficulty. However, the impact of wafer thinning on chip performance has not been fully clarified.

This study analyzes the electrical characteristics before and after thinning wafers of FRAM, HP Logic, and DRAM, reducing the wafer thickness to below 10 µm, and explores the impact of ultra-thinning processes on chip performance.

1. Introduction

The miniaturization of semiconductor chips is facing a significant turning point in technology and economics. 3D stacking technology utilizes TSVs to achieve vertical interconnection of chips, which is one of the important ways to overcome the bottleneck of miniaturization. 3D stacked chips connect multiple chips through vertical TSVs (Figure 1), significantly improving chip bandwidth, shortening connection line lengths, reducing parasitic resistance and capacitance, lowering power consumption, and achieving smaller package sizes, making them more suitable for mobile devices.

In 3D stacked chips, chip thinning becomes essential. Additionally, using ultra-thin wafers can achieve low aspect ratio TSVs (Figure 2), further enhancing chip performance and manufacturing efficiency.

However, the specific impact of chip thinning on electrical performance remains unclear, so this study deeply analyzes the impact of thinning on the electrical characteristics of FRAM, HP Logic, and DRAM chips.

2. Wafer Thinning Process

The silicon wafer thinning process consists of two main steps: back grinding (BG) and stress relief (Figure 3).

• Back Grinding (BG):Stepwise grinding using grinding wheels of different particle sizes, coarse grinding (#320) and fine grinding (#2000) gradually reach the target thickness.

• Stress Relief:Typically uses Ultra Poligrind (UPG), Chemical Mechanical Polishing (CMP), or dry polishing (DP) to remove the damage layer generated during grinding.

Through μ-Raman spectroscopy analysis (Figure 4) and Positron Annihilation Spectroscopy (Figure 5), the residual stress and lattice defect conditions on the wafer surface after grinding were studied. The research found that after CMP, the wafer had almost no residual stress and defects, while the wafer after fine grinding still had some damage.

3. Experimental Methods and Processes

This study used the WOW (Wafer-on-a-Wafer) process (Figure 6) for wafer thinning treatment and electrical characteristic evaluation, selecting three types of chips for testing:

• FRAM (Ferroelectric Random Access Memory), 180-nm process node

• HP Logic (High-Performance Logic Chip), 45-nm process node

• DRAM (Dynamic Random Access Memory), 40-nm process node

Experimental process:

1. Temporarily bonding the wafer to a support substrate for thinning from the back;

2. Selecting different stress relief methods (CMP, UPG, no treatment) based on chip type;

3. After thinning, transferring the chip to a permanent substrate for electrical performance evaluation.

The target wafer thicknesses are:

• FRAM: 9 µm

• HP Logic: 7 µm

• DRAM: 4~40 µm

4. Results and Discussion

• FRAM Performance Evaluation (Figure 7):FRAM thinned to 9 µm thickness showed no significant degradation in the hysteresis characteristics of the ferroelectric memory, indicating that thinning and wet processing did not adversely affect FRAM performance.

• HP Logic Performance Evaluation (Figure 8):HP Logic chips thinned to 7 µm showed no degradation in current driving characteristics, indicating that the residual stress and defects after thinning did not significantly affect chip performance.

• DRAM Performance Evaluation (Figures 9, 10):When DRAM chips were ultra-thinned to 4 µm, the overall thickness uniformity (TTV) reached an excellent level of 1.02 µm. Furthermore, even when thinned to 4 µm, the retention performance of DRAM showed no significant changes, indicating that ultra-thinning does not compromise chip reliability.

5. Conclusion and Outlook

Through the analysis of the electrical performance of FRAM, HP Logic, and DRAM chips, this study confirms that ultra-thinning treatment of wafers to 4 µm does not cause significant negative impacts on chip performance. The research also shows:

• Ultra-thin wafers can further shorten the wiring lengths between chips, effectively reducing parasitic resistance and capacitance.

• It can achieve lower power consumption, higher reliability, and smaller package sizes.

DISCO will continue to optimize and advance ultra-thin wafer processing technology to better meet the needs of future semiconductor manufacturing processes.

📚 Quick Interpretation of Technical Terms:

🔑 TSV (Through Silicon Via)A vertical hole through the silicon substrate used to connect multiple chip layers for 3D stacking.

🔑 Low-k Dielectric FilmA low dielectric constant insulating film material used to reduce parasitic capacitance within the chip.

🔑 Back Grinding (BG)A thinning process performed on the back side of the wafer, typically used to reduce wafer thickness.

🔑 Stress ReliefA process that removes the damage layer on the wafer surface through special grinding or polishing techniques, eliminating processing stress and enhancing chip reliability.

🔑 Retention Characteristics (DRAM Charge Retention)The ability of capacitors in DRAM chips to hold charge, which relates to the reliability of data storage.

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Author:Device Salesman and Brazilian Jiu-Jitsu PractitionerCurrently residing in: Tokyo, JapanJob: Semiconductor Equipment Trading Company Sales & Website ManagementStudying: Keio University Faculty of Economics & Akita University Faculty of Science and EngineeringInterests: Brazilian Jiu-Jitsu (Brown Belt, practicing for 14 years)

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