Introduction:
The quality design and control during the semiconductor product development phase is crucial for ensuring product success, high reliability, and cost-effectiveness. For large semiconductor companies (such as Toshiba, ON, Samsung, Renesas, Vishay, ADI, etc.), this is not merely about simple quality inspection, but rather a systematic engineering process that spans the entire product lifecycle.
Below is an overview of how major manufacturers conduct quality design and control during the semiconductor product development phase.Overview
1. Design-in Quality Methods
1.1 Reliability Design (DfR) and Design for Manufacturability (DfM)
|
Company |
Core Measures |
Technical Details and Data Metrics |
|
Renesas |
Microfabrication Design Optimization |
– Yield improvement of 15% using advanced processes below 0.13μm (electromigration optimization) – Change review coverage of 100% design nodes, defect review rate decreased by 40% |
|
Sharp |
Design Embedded Reliability |
– Defect detection rate of 92% during Design Review (DR) phase – Reliability assessment covers JEDEC JESD47 standards, early failure <1 DPPM |
|
Sony |
Goal-Oriented Design |
– Quality target quantification: e.g., CMOS image sensor dark current ≤0.5nA/cm² – FMEA assessment RPN (Risk Priority Number) >100 must be rectified 100% |
1.2 Failure Prevention Tools
|
Company |
Tool Application |
Data Control Standards |
|
ON Semiconductor |
DFMEA+PPAP |
– DFMEA coverage: 100% for automotive projects – PPAP document compliance rate ≥98% (including MSA, CPK data) |
|
Toshiba |
TEG Failure Analysis |
– TEG test structure exceeds 5000 sets/chip – Acceleration factor model: temperature (Arrhenius model) Ea=0.7eV, voltage Vacc=1.5×Vdd |
2. Standardized Control of Development Processes
2.1 Phase-Gate Process
ON Semiconductor APQP five-phase control (data source: IATF 16949)
|
Phase |
Key Deliverables |
Quality Threshold Standards |
|
Concept |
Technical Feasibility Report |
Yield simulation ≥85% |
|
Development |
Design Verification (DV) |
Parameter compliance rate 100% (±3σ) |
|
Certification |
AEC-Q100 Test Report |
Grade 1 standard: HTOL 1000 hours @125℃, FIT rate <10 |
2.2 Design Review (DR) and Prototype Verification
Renesas DR process depth
2.3 Reliability Testing System
ADI Qualification Plan framework
|
Test Category |
Project |
Execution Standards |
Criteria |
|
Life Testing |
HTOL |
JESD22-A108 |
Failure count ≤0/77 samples |
|
Environmental Testing |
HAST |
JESD22-A110 |
168 hours @130℃/85%RH |
|
Mechanical Testing |
Shock |
MIL-STD-883G |
1500G, 0.5ms |
3. Quality Verification Mechanism Before Mass Production
3.1 Early Warning System
Renesas initial control model for mass production
•Data collection frequency: full inspection of key parameters every hour
•Response time: ≤4 hours (including 8D report initiation)
•First month DPPM target: ≤500
3.2 Statistical Process Control (SPC)
Sharp trial production control model
•Key parameter monitoring: Cpk≥1.67 (one-sided specification)
•Out-of-control action limits:
¡Warning: 7 consecutive points exceeding ±1.5σ → process adjustment
¡Line stop: 3 consecutive points exceeding ±3σ → freeze batch number
Sony SPC index application comparison
|
Index |
Usage |
Target Value |
|
Cp |
Short-term potential |
≥1.33 |
|
Cpk |
Actual deviation |
≥1.25 |
|
Pp |
Long-term potential |
≥1.0 |
|
Ppk |
Long-term deviation |
≥0.9 |
4. Common Practices Across Enterprises
4.1 In-depth Analysis of Standard Compliance
|
Standard |
Development Phase Embedding Points |
Review Data Requirements |
|
IATF 16949 |
DFMEA/CP (Control Plan) |
RPN closed-loop rate 100% |
|
ISO 9001:2015 |
Design Verification Records |
Document traceability ≥99% |
|
AEC-Q100 Rev-H |
Grade 2 Certification |
HTOL failure count = 0/77 |
4.2 Knowledge Reuse Technical Pathways
Sony Failure Case Library Application
•Rule library scale: over 5000 entries (including electrostatic protection, thermal design, etc.)
•DRC error interception rate: improved by 60%
4.3 Supply Chain Collaboration Quantitative Requirements
ON Semiconductor Supplier Admission Standards
|
Item |
Audit Items |
Compliance Value |
|
Equipment Capability |
Photolithography Alignment Accuracy |
≤3nm (3σ) |
|
Process Stability |
Cpk (Etch Rate) |
≥1.50 |
|
Personnel Qualifications |
6σ Green Belt Certification Coverage |
≥30% |
Conclusion: Industry-Level Quality System Technical Indicators
1.Design Prevention Indicators
•FMEA coverage: 100% for automotive projects, ≥80% for consumer products
•Simulation and actual measurement deviation: ≤5% (based on SPICE model)
2.Process Control Indicators
•Phase gate pass rate: first time ≤60% (mandatory iterative optimization)
•Prototype test first-pass yield: ≥90% (automotive grade)/≥85% (consumer grade)
3.Mass Production Verification Indicators
•Early warning efficiency: first month issue closure rate ≥95%
•SPC out-of-control events: ≤2 times/quarter
4.Knowledge System Indicators
•Rule library update frequency: ≥50 entries/quarter
•Annual supplier audits: non-conformities ≤3 items
Data Source Notes:
1. All indicators are based on corporate practices in the original document, supplemented by JEDEC/AECQ/IATF industry standard data;
2. Data sourced from various companies’ quality manuals and reliability policies;
3. Cited the SEMI defect cost report from the software industry.
△ Learning Framework:
