IP and SoC Simulation and Debugging of OpenTitan

Project Introduction

Path

<span>/home/IC_verify/project/opentitan</span>

Simulation Prerequisites and Notes

1.Before running the simulation, execute source ~/source_python to switch the default Python version.2.Do not modify any files in Bazel; only run the simulation. Otherwise, Bazel will determine that dependencies need to be updated, leading to errors when downloading libraries.

Simulation Method

IP Verification

Hardware IP Blocks – OpenTitan Documentation

https://opentitan.org/book/hw/ip/index.html

IP List

IP and SoC Simulation and Debugging of OpenTitanTaking AES as an example Directory:

 /home/IC_verify/project/opentitan/hw/ip/aes/dv

Case List: (Find files ending with hjson)IP and SoC Simulation and Debugging of OpenTitanTestplan Breakdown for Cases

Testplan – OpenTitan Documentation

https://opentitan.org/book/hw/ip/aes/data/aes_testplan.html

Simulation Command: (Select one of the aes_smoke)IP and SoC Simulation and Debugging of OpenTitan

 util/dvsim/dvsim.py hw/ip/aes/dv/aes_unmasked_sim_cfg.hjson -i aes_smoke --waves fsdb --tool vcs

Simulation Process:

IP and SoC Simulation and Debugging of OpenTitan

Simulation Directory:

IP and SoC Simulation and Debugging of OpenTitan

SoC Verification

Top Earlgrey – OpenTitan Documentation

https://opentitan.org/book/hw/top_earlgrey/index.html

IP and SoC Simulation and Debugging of OpenTitan

Case List

https://opentitan.org/book/hw/top_earlgrey/data/chip_testplan.html

Simulation Command

util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i &lt;Select case from the case list&gt; --waves fsdb

Select one case for simulation

IP and SoC Simulation and Debugging of OpenTitan

util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_uart_tx_rx --waves fsdb

Waveform Debugging

IP and SoC Simulation and Debugging of OpenTitan

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