Research Guide on Carrier-Supported Copper Foil, Coreless Support, and PCB Manufacturing Methods

1. Overview and Core Concepts

This research guide aims to provide an in-depth understanding of carrier-supported copper foil and its applications in coreless support and printed circuit board (PCB) manufacturing. The focus is on a novel design of carrier-supported copper foil that addresses the issues of poor delamination stability and insufficient developer resistance in existing technologies by introducing a specific intermediate layer.

Core Invention Points:

• Structure of Carrier-Supported Copper Foil: Carrier, intermediate layer, release layer, ultra-thin copper layer (optional anti-reflective layer).
• Key Role of the Intermediate Layer: Improves adhesion stability between the carrier and release layer, enhances developer resistance, prevents the intermediate layer from delaminating, thus optimizing wiring pattern formation. The intermediate layer can be a single alloy layer or a two-layer structure (adhesion metal layer and release assist layer).
• Coreless Lamination Method: A PCB manufacturing method that does not use a core substrate, achieving multilayering by alternately stacking insulation layers and wiring layers.
• RDL-First Method: A process where a wiring layer is formed on the surface of the coreless support before chip installation, helping to improve yield and economic benefits.

2. Structure and Composition of Carrier-Supported Copper Foil

1. Carrier (12)

• Material Selection: Glass, ceramics, resins, metals, etc. Preferred materials are those with low CTE, such as polyimide resin, liquid crystal polymer, glass, and ceramics.
• Preferred Material Properties: Thermal expansion coefficient (CTE) below 25 ppm/K, Vickers hardness above 100 HV. Glass, especially alkali-free glass, is particularly preferred.
• Thickness: Preferably 100–2000 μm, more preferably 300–1800 μm, and further preferably 400–1100 μm.
• Surface Roughness (Ra): Preferably 0.1–70 nm, which helps in forming fine wiring patterns.
• End Face Coverage: The intermediate layer, release layer, anti-reflective layer, and ultra-thin copper layer preferably cover the carrier’s end face to prevent chemical solution intrusion and gaps during operation.

2. Intermediate Layer (14)

• Function: Ensures adhesion between the carrier and release layer, provides delamination stability, and enhances resistance to developer solutions.
• Composition Requirements: The carrier side surface contains at least one metal (Metal M) from Ti, Cr, Mo, Mn, W, and Ni in an amount of 1.0 at% or more; the opposite side surface contains at least 30 at% Cu.
• Thickness: Preferably 5–1000 nm.
• Layer Composition: Single Layer (Intermediate Alloy Layer): Composed of an alloy of Metal M and Cu, with Metal M content of 1.0 at% or more and Cu content of 30 at% or more.
• Two-Layer Composition: Adhesion Metal Layer (14a): Located on the carrier, composed of at least one metal from Ti, Cr, Mo, Mn, W, and Ni. Ti is preferred. Thickness is preferably 5–500 nm.
• Release Assist Layer (14b): Located on the adhesion metal layer, composed of copper, with Cu content preferably 50–100 at%. Thickness is preferably 5–500 nm.

3. Release Layer (16)

• Function: Enables the release of the carrier (and intermediate layer).
• Material Selection: Organic or inorganic release layers. Preferably an inorganic release layer mainly composed of carbon (carbon layer), especially amorphous carbon.
• Carbon Concentration: Preferably above 60 at%.
• Thickness: Preferably 1–20 nm.

4. Anti-Reflective Layer (17) (Optional)

• Function: Prevents light reflection, improves recognition in image inspection (AOI), and has chemical resistance to copper etching solutions.
• Material Selection: Composed of at least one metal from Cr, W, Ta, Ti, Ni, and Mo. Preferred are Ta, Ti, Ni, and Mo, with Ti being the most preferred.
• Surface Properties: The surface of the ultra-thin copper layer side is a collection of metal particles, appearing dark in color.
• Glossiness (Gs(60°)): Preferably below 500.
• Projected Area Equivalent Diameter: Preferably 10–100 nm.
• Oxygen Content: Preferably 0–15 at%, essentially unoxidized.
• Thickness: Preferably 1–500 nm.

5. Ultra-Thin Copper Layer (18)

• Function: Serves as the foundation for the wiring layer.
• Manufacturing Method: Wet film formation method (chemical copper plating, electroplating) or vapor phase deposition method (sputtering, vacuum deposition, ion plating), with sputtering being preferred.
• Thickness: Preferably 50–3000 nm, more preferably 150–500 nm.
• Surface Roughness (Ra): Preferably 1.0–100 nm, which helps in forming fine wiring patterns.

3. Manufacturing Methods

1. Manufacturing Method of Carrier-Supported Copper Foil

• Main Method: Vapor phase method, preferably sputtering.
• Sputtering Conditions: Target material selection, non-oxidizing atmosphere, sputtering pressure (0.1–20 Pa), sputtering power (0.05–10.0 W/cm²), film formation temperature (25–300℃).
• End Face Coverage Implementation: Achieved by exposing the end face of the carrier during film formation on the substrate.

2. Manufacturing Method of Coreless Support with Wiring Layer

1. Process: Preparation of Carrier-Supported Copper Foil: Prepare the carrier-supported copper foil with the above structure.
2. Photoresist Layer Formation: Form a photoresist layer (e.g., photosensitive dry film) on the surface of the ultra-thin copper layer in a specified pattern.
3. Electroplated Copper Layer Formation: Form an electroplated copper layer on the exposed portion of the ultra-thin copper layer.
4. Photoresist Layer Removal: Remove the photoresist layer, exposing the portions of the ultra-thin copper layer where the wiring pattern has not been formed.
5. Copper Flash Etching: Remove the unnecessary portions of the ultra-thin copper layer to form the wiring layer. If an anti-reflective layer is present, it will be exposed and remain after copper flash etching.
6. Image Inspection (Optional): Perform AOI inspection on the wiring layer; the anti-reflective layer can improve recognition.
7. Electronic Component Mounting (Optional): Mount chips and other electronic components on the wiring layer (RDL-First method).

3. Manufacturing Method of Printed Circuit Boards

1. Process: Manufacturing of Coreless Support with Wiring Layer: Same as the above method.
2. Manufacturing of Laminated Structure with Layered Material: Form a layered structure (e.g., prepreg and copper foil stacked and cured) on the wiring layer.
3. Separation of Laminated Structure with Layered Material: Separate the carrier, intermediate layer, and release layer through the release layer to obtain a multilayer PCB. Physical separation is preferred.

• Processing of Multilayer PCB: Removal of Anti-Reflective Layer: If an anti-reflective layer exists, remove it through selective flash etching to expose the wiring layer. The etching solution selection depends on the anti-reflective layer material.
• Outer Layer Processing: Further stack insulation layers and wiring layers, or form a solder mask, perform surface treatment (Ni-Au plating, OSP treatment, etc.), or set up pillar supports.

4. Evaluation Indicators

• Resistance of Ultra-Thin Copper Layer to Developer Solutions: Evaluate the degree of delamination of the ultra-thin copper layer caused by the immersion of developer solutions at the interlayer interface (especially between the release layer and adhesion metal layer).
• Delamination of Carrier-Ultra-Thin Copper Layer: Determine the delamination strength after thermal treatment to assess delamination stability.
• Coating Gaps in Coreless Support End: Assess the integrity of the coating (ultra-thin copper layer and anti-reflective layer) at the side end during operation or processing.
• Formation of Fine Patterns in Embedded Wiring Layer: Evaluate the integrity of the wiring pattern after forming the multilayer board, especially the defect rate such as short circuits.
• Chemical Solution Intrusion Width: Assess the degree of chemical solution intrusion into the carrier during PCB manufacturing processes (e.g., desmear treatment).

Exercises and Tests

1. Short Answer Questions (2-3 sentences each)

1. Please briefly describe the core function of the “intermediate layer” in the novel carrier-supported copper foil.
2. Why are materials with low thermal expansion coefficients (CTE) preferred for the carrier material selection in carrier-supported copper foil?
3. What is the reason for preferring Ti over Al in the composition of the adhesion metal layer (14a)?
4. Why is the thickness of the release layer (16) limited to a thin range of 1-20 nm when primarily composed of carbon?
5. What are the two main functions of the anti-reflective layer (17) in carrier-supported copper foil?
6. Explain why the etching solution can stop at the anti-reflective layer during the copper flash etching process.
7. What economic advantages does the RDL-First method have over the Chip-First method?
8. Why does the intermediate layer provide excellent stability for the mechanical delamination strength of the carrier when separating the laminated structure?
9. Please describe the advantages of the sputtering method in manufacturing the layers of carrier-supported copper foil.
10. What is the importance of covering the carrier’s end face with various layers, especially during PCB manufacturing?

2. Answer Key

1. The main function of the intermediate layer is to significantly enhance the stability of adhesion between the carrier and the release layer, providing excellent resistance to developer solutions. It effectively prevents the intermediate layer from detaching during the separation of the coreless support or carrier, ensuring stability in the subsequent wiring pattern formation process.
2. Choosing carrier materials with low thermal expansion coefficients (CTE) is to effectively prevent warping of the coreless support during the mounting of electronic components (such as chips) due to heating. A lower CTE means less dimensional change with temperature variations, maintaining the flatness and dimensional stability of the PCB.
3. Ti is preferred over Al as the adhesion metal layer (14a) because Ti better ensures adhesion between the carrier and the adhesion metal layer as well as the release assist layer. Additionally, Ti significantly prevents delamination of the ultra-thin copper layer during the formation of the wiring layer on the coreless support and prevents detachment of the adhesion metal layer and release assist layer when delaminating the coreless support or carrier, resulting in better processing performance.
4. The release layer (16) is limited to a thin range of 1-20 nm to ensure effective delamination of the carrier. A thin release layer also facilitates uniform and precise thickness control through methods like sputtering, maintaining good film formation and ease of delamination.
5. The two main functions of the anti-reflective layer (17) are: first, to prevent light reflection, making its surface appear dark, thus providing the desired visual contrast with the copper wiring layer during image inspection (e.g., AOI); second, its metallic composition is insoluble in copper flash etching solutions, giving it excellent chemical resistance.
6. The anti-reflective layer can stop copper flash etching because its metallic components (such as Cr, W, Ta, Ti, Ni, and Mo) are insoluble in copper flash etching solutions. This means that when the copper flash etching solution removes the exposed ultra-thin copper layer, it encounters the anti-reflective layer and stops etching, thus protecting the underlying wiring layer.
7. The economic advantage of the RDL-First method is that it allows for image inspection of the wiring layer on the coreless support surface before chip installation. This enables manufacturers to identify and avoid defective wiring sections, installing expensive chips only on good sections, significantly reducing unnecessary chip usage and waste, thus improving overall product yield.
8. The intermediate layer provides excellent stability for the mechanical delamination strength of the carrier by constructing a controlled adhesion interface between the carrier (such as glass or ceramics) and the release layer. The specific metals (Metal M) on the carrier side ensure good adhesion with the carrier, while the Cu on the release layer side forms lower adhesion with the release layer (such as carbon). This design allows the carrier to separate stably and uniformly from the entire surface during delamination, avoiding local tearing or residue, thus preventing detachment of the intermediate layer.
9. The advantages of the sputtering method in manufacturing the layers of carrier-supported copper foil include its ability to achieve precise thickness control over a wide range from 0.05 nm to 5000 nm and ensure uniformity of film thickness over large areas. Additionally, the sputtering method has a fast deposition rate and high productivity, which is very beneficial for large-scale industrial production.
10. The importance of covering the carrier’s end face with various layers lies in its ability to effectively prevent chemical solution intrusion into the carrier during PCB manufacturing processes. Moreover, this coverage design also strongly prevents gaps or cuts in the coating (ultra-thin copper layer and anti-reflective layer) at the side ends during the operation of the coreless support (e.g., during roller transport), thus protecting the integrity of the product edges.

3. Thesis Format Issues (No Answers Provided)

1. Detail how the different metal element content requirements in the intermediate layer (whether single alloy or dual-layer structure of adhesion metal layer/release assist layer) work synergistically to achieve excellent developer resistance and stability of mechanical delamination strength of the carrier.
2. Analyze how the structure of the carrier-supported copper foil in this invention (especially the intermediate layer and anti-reflective layer) specifically addresses the challenges faced by traditional coreless lamination methods in miniaturization and RDL-First processes (such as delamination instability, low recognition in image inspection, warping, etc.).
3. Compare the advantages and disadvantages of using the sputtering method to manufacture ultra-thin copper layers and anti-reflective layers with traditional wet film formation methods or vapor deposition methods, and discuss the impact of sputtering parameters (such as pressure, power, temperature) on the film characteristics (such as roughness, particle size, element content) of each layer.
4. Discuss the interaction mechanisms between the release layer, intermediate layer, and anti-reflective layer during PCB manufacturing processes, and how these layers behave in various processes (such as photoresist development, copper flash etching, delamination, desmear) to ensure high quality and reliability of the final product.
5. Combine tabular data to analyze the impact of different carrier materials (such as glass, alumina, yttria-stabilized zirconia) on the performance of carrier-supported copper foil (such as delamination, resistance to developer solutions, chemical solution intrusion width, and formation of embedded wiring patterns), and propose future optimization directions.

4. Glossary of Keywords

• Carrier-Supported Copper Foil: A composite material consisting of a carrier, intermediate layer, release layer, and ultra-thin copper layer, used for manufacturing precision printed circuit boards.
• Coreless Support: In multilayer PCB manufacturing, a support structure formed by stacking insulation layers and wiring layers without using a traditional core substrate.
• Printed Circuit Board (PCB): A circuit board that serves as a carrier for electronic components, connecting various electronic elements.
• Intermediate Layer: A layer set between the carrier and release layer, enhancing interlayer adhesion and delamination stability, and providing key resistance to developer solutions.
• Release Layer: A layer set on top of the intermediate layer, allowing the carrier (along with the intermediate layer) to be effectively released in subsequent processes.
• Ultra-Thin Copper Layer: An ultra-thin copper layer set on the release layer or anti-reflective layer, serving as the foundation for forming wiring patterns.
• Anti-Reflective Layer: An optional layer set between the release layer and ultra-thin copper layer, used to reduce light reflection, improve recognition in image inspection, and provide resistance to copper flash etching solutions.
• Carrier: The substrate supporting the multilayer structure of carrier-supported copper foil, which can be made of glass, ceramics, resins, or metals.
• Adhesion Metal Layer: A sublayer in the intermediate layer that directly contacts the carrier, composed of specific metals (such as Ti, Cr, Mo, Mn, W, Ni) to ensure good adhesion with the carrier.
• Release Assist Layer: A sublayer in the intermediate layer, set on top of the adhesion metal layer, mainly composed of copper, assisting in achieving stable delamination.
• Intermediate Alloy Layer: A single-layer intermediate structure composed of an alloy of specific metal M and Cu.
• Vapor Phase Method: A method of depositing thin films on substrates through materials in gas or vapor form, such as sputtering, vacuum deposition, and ion plating.
• Sputtering Method: A physical vapor deposition (PVD) technique that uses ion bombardment to sputter atoms from a target material and deposit them onto a substrate to form a thin film.
• Magnetron Sputtering: An improved sputtering technique that uses a magnetic field to enhance ionization efficiency and accelerate deposition rates.
• Coreless Lamination Method: A method for manufacturing multilayer PCBs characterized by not using a core substrate, with insulation layers and wiring layers alternately stacked.
• RDL-First Method: An advanced packaging process where a wiring layer is formed on the surface of the coreless support before chip installation.
• Chip-First Method: A traditional packaging process where chips are installed first, followed by the formation of wiring layers on their surface.
• Photoresist: A light-sensitive material used to form desired patterns through exposure and development.
• Developer Solution: A chemical solution used to selectively dissolve the unexposed or exposed portions of the photoresist to form patterns.
• Copper Flash Etching: A chemical etching process used to quickly remove unwanted portions of the ultra-thin copper layer.
• Automated Optical Inspection (AOI): An automated optical inspection technology used to detect defects in PCB wiring patterns.
• Laminate: In PCB manufacturing, a structure formed by stacking multiple materials (such as wiring layers and insulation layers) together.
• Desmear: A chemical treatment step in PCB manufacturing used to remove resin residues from drilled hole walls to ensure the quality of subsequent copper plating.
• Coefficient of Thermal Expansion (CTE): The rate at which a material’s length or volume changes with temperature variations.
• Vickers Hardness: A standard for measuring material hardness, determined by pressing a diamond indenter into the material’s surface and measuring the size of the indentation.
• Arithmetic Average Roughness Ra: An indicator of surface roughness, representing the arithmetic average of the absolute values of the profile deviations over a measured section.
• Projected Area Equivalent Diameter: The diameter equivalent of a circle derived from the projected area of particles through image analysis.