Five Fundamental Skills for Successful FPGA Design

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To become a competent FPGA designer, one must master five fundamental skills: simulation, synthesis, timing analysis, debugging, and verification.

It is important to emphasize that these fundamental skills are for FPGA designers, not for IC designers. I do not understand IC design, so I dare not make any claims.

For FPGA designers, mastering these five fundamental skills is part of the same process as effectively using the corresponding EDA tools, as follows:

  1. Simulation: Modelsim, Quartus II (Simulator Tool)

  2. Synthesis: Quartus II (Compiler Tool, RTL Viewer, Technology Map Viewer, Chip Planner)

  3. Timing: Quartus II (TimeQuest Timing Analyzer, Technology Map Viewer, Chip Planner)

  4. Debugging: Quartus II (SignalTap II Logic Analyzer, Virtual JTAG, Assignment Editor)

  5. Verification: Modelsim, Quartus II (Test Bench Template Writer)

Mastering HDL languages is not everything in FPGA design, but the influence of HDL languages runs throughout the entire FPGA design process and complements the five fundamental skills of FPGA design.

For FPGA designers, effectively using the synthesizable subset of HDL can accomplish 50% of the FPGA design work—design coding.

Mastering simulation, synthesis, and timing analysis, the three fundamental skills, can aid in learning the synthesizable subset of HDL in the following ways:

  1. Through simulation, one can observe the logical behavior of HDL in the FPGA.

  2. Through synthesis, one can observe the physical implementation of HDL in the FPGA.

  3. Through timing analysis, one can analyze the physical implementation characteristics of HDL in the FPGA.

For FPGA designers, effectively using the verification subset of HDL can accomplish the other 50% of the FPGA design work—debugging and verification.

  1. Establish a verification environment, and through simulation, one can verify the correctness of the FPGA design.

  2. Comprehensive simulation verification can reduce the workload of FPGA hardware debugging.

  3. By combining hardware debugging with simulation verification methods, one can use debugging to resolve issues not verified by simulation and use simulation to ensure that resolved issues do not reappear in debugging, establishing a regression verification process that aids in the maintenance of FPGA design projects.

Five Fundamental Skills for Successful FPGA DesignWant to learn about FPGA? Here are example shares, ZYNQ design, follow our public account to explore.

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