In the “black technology” of chip manufacturing, there is a technique specifically designed to “boost” NMOS (a key transistor), known as source-drain embedded SiC strain technology. For those looking to get started in chip manufacturing, this is a crucial knowledge point for understanding advanced processes! Today, we will break it down clearly, allowing you to see through the underlying logic of this technology at a glance.
1. Why Boost NMOS?
In advanced chip processes of 90nm and below, engineers are constantly striving to enhance the speed of NMOS. Source-drain embedded SiC strain technology is one of the “ace techniques”—it applies special stress to the channel, allowing electrons to move faster and more smoothly within the channel.
2. The “Magical Principle” of SiC Strain Technology: The Clever Use of Lattice Mismatch
To understand this technique, one must first grasp the relationship between lattice constants and stress.
– The lattice constant of silicon (Si) is 5.431Å (Å is a unit of length, 1Å = 0.1 nanometers), while that of carbon (C) is 3.57Å. The “mismatch rate” between the two is as high as 34.27%!
– When SiC (silicon carbide) material is embedded using epitaxial growth technology on a silicon substrate, the smaller lattice constant of SiC compared to pure silicon creates tensile stress on the surrounding silicon channel, effectively “stretching” the channel’s lattice. This stress alters the energy band structure of the silicon conduction band, reducing the effective mass of electrons (which can be understood as a decrease in resistance to electrons “running” in an electric field) and simultaneously decreasing the probability of electron scattering (akin to reducing the number of “obstacles” encountered by electrons on the track). As a result, electrons move faster and more smoothly, naturally increasing the speed of NMOS!
3. NMOS’s Exclusive “Speed Boost Package”: Precision of Uniaxial Tensile Stress
NMOS channels are manufactured in the [100] crystal orientation (a specific direction in the chip’s crystal structure). When SiC strain material is embedded in the source-drain, uniaxial tensile stress is generated in the [100] direction.
– This stress aligns the “main energy valley isoelectronic surface” axis perpendicular to the channel direction, significantly reducing the “running resistance” of electrons along the channel direction.
– In simple terms, it paves a “highway” for electrons in the channel direction, enhancing both the switching speed and driving capability of NMOS.
4. How to Accurately “Embed” SiC? The Art of Selective Epitaxial Growth (SEG) Technology
To accurately embed SiC in the source-drain region, one must rely on Selective Epitaxial Growth (SEG) technology. The core logic is:
– Utilizing the characteristic that “silicon is difficult to film on insulators,” SiC epitaxial layers are only grown in specific areas on the silicon surface (the source-drain region), while insulating regions (such as STI isolation areas) do not grow.
– The principle is that silicon has almost no nucleation on SiO₂ (silicon dioxide), and nucleation on Si₃N₄ (silicon nitride) is also more difficult than on silicon. Therefore, atoms landing on the insulator will “migrate” to the silicon single crystal area where nucleation is easier, ultimately resulting in SiC growth only in the silicon region of the source-drain.
5. Process Challenges and Solutions: Multiple Depositions + Millisecond Annealing
Of course, this technology is not “plug-and-play”; it has two major challenges:
Challenge 1: Poor selectivity of SiC epitaxy
When SiC grows in the source-drain groove, it easily grows on the oxide (such as sidewalls, STI) as well. Solution: Use a cycle process of CVD deposition + wet etching. CVD can grow single-crystal SiC films on single-crystal silicon substrates, while non-crystalline SiC films grow on oxides. Non-crystalline SiC has a high etching rate, and through multiple “deposition-etching” cycles, the desired thickness of single-crystal SiC can be accurately grown on the single-crystal silicon of the source-drain.
Challenge 2: Poor thermal stability of SiC
During high-temperature annealing above 900°C, carbon atoms in SiC can “escape” from their original lattice positions, leading to a loss of stress (the more carbon atoms that leave, the faster the stress is lost). Solution: Employ millisecond annealing technology to strictly control the high-temperature duration, reducing the “escape” of carbon atoms.
6. Complete Process Flow for NMOS Source-Drain Embedded SiC (Step-by-Step Breakdown)
Combining Figure 2-9, let’s look at how this technology is implemented step by step:
1. Starting Process: First, complete the manufacturing of the sidewalls and LDD (lightly doped drain) structure.
2. Deposit Barrier Layer: Use LPCVD to deposit a layer of SiO₂ oxide as a “forbidden zone marker” for subsequent SiC epitaxy.
3. Photolithography and Etching Windows: Through photolithography and etching, remove SiO₂ in the NMOS region to expose the “window” for SiC growth.
4. Etch Source-Drain Groove: Selectively etch the silicon substrate to create a groove at the NMOS source-drain position, making room for SiC growth.
5. Cycle Growth + Doping: Through multiple CVD depositions and wet etching, grow a single-crystal SiC film on the silicon substrate of the source-drain groove while performing n-type phosphorus doping (to give SiC conductivity).
Conclusion: Small SiC Gives Chips Wings of Speed
Source-drain embedded SiC strain technology enables NMOS in processes of 90nm and below to achieve a speed leap through a series of operations: “stress generated by lattice mismatch → optimization of electron transport characteristics → precise selective epitaxy growth → overcoming process challenges.” For beginners in chip manufacturing, understanding this technology allows one to grasp the threshold of the “speed logic” in advanced processes. Every technology in chip manufacturing is like a precise gear, and SiC strain technology is a key component driving the “speed gear.” If you want to delve deeper into the world of chips, this kind of “hardcore knowledge” must be thoroughly understood!