1. Overview
In the article “CPU Architecture,” we introduced the three major families of instruction set architectures: <span>x86 family</span>, <span>ARM family</span>, and <span>RISC-V</span>.
Did you know that the ARM instruction set also includes three different series: <span>Cortex-A</span>, <span>Cortex-R</span>, and <span>Cortex-M</span>? Are you aware of the differences and relationships between these three series of processor cores? This article will provide you with a detailed understanding.
These three series are designed for different application domains and can be simply understood as:
- Cortex-A: The brain responsible for “thinking” and “interaction.” It pursues high performance and runs complex operating systems.
- Cortex-R: The spinal cord responsible for “reaction” and “control.” It emphasizes high real-time performance and reliability, used for critical task control.
- Cortex-M: The peripheral nervous system responsible for “sensing” and “action.” It aims for extreme energy efficiency and low cost, used for micro embedded control.
Note: An interesting fact is that the letters of these three series (A, R, and M) combine to form ARM.
Next, we will compare them in detail from multiple dimensions.
2. Core Positioning
| Series | Full Name | Core Positioning | Typical Application Scenarios |
|---|---|---|---|
| Cortex-A | Application | Application Processor. Focused on high performance and high computational power, aimed at running complex operating systems and rich user applications. | Smartphones, tablets, smart TVs, set-top boxes, servers, automotive infotainment systems, single-board computers (like Raspberry Pi). |
| Cortex-R | Real-time | Real-time Processor. Focused on high real-time performance, high reliability, and fault tolerance, used for critical tasks with strict response time requirements. | Automotive braking systems, powertrains, airbags, hard disk/SSD controllers, industrial control, network device baseband processing. |
| Cortex-M | Microcontroller | Microcontroller. Focused on ultra-low power consumption, minimal chip area, and low cost, used for resource-constrained embedded systems and IoT devices. | Smartwatches, smart home devices (sensors, bulbs), drone flight control, motor control, IoT terminals, toys, keyboards, and mice. |
3. Architecture and Technical Features
| Feature | Cortex-A | Cortex-R | Cortex-M |
|---|---|---|---|
| Architecture | Typically ARMv7-A or ARMv8-A / ARMv9-A (supports 64-bit) | Typically ARMv7-R or ARMv8-R | Typically ARMv6-M, ARMv7-M, ARMv8-M |
| Memory Management (MMU/MPU) | Full MMU (Memory Management Unit) | Optional MPU (Memory Protection Unit) | Typically only MPU (even not available in low-end models) |
| Interrupt Handling | Uses GIC (Generic Interrupt Controller), higher interrupt response latency | Optimized interrupt controller, extremely low and predictable interrupt latency | Integrated NVIC (Nested Vector Interrupt Controller), extremely low interrupt latency, entry-level |
| Pipelining | Long and complex (superscalar, out-of-order execution) to enhance performance | Medium length, deeply optimized for determinism (predictable instruction execution time) | Very short (3-stage pipelines are common), simple, pursuing energy efficiency and determinism |
| Operating System Support | Linux, Android, Windows and other rich operating systems | RTOS (like FreeRTOS, VxWorks), determinism is key | RTOS (like FreeRTOS, Zephyr, μC/OS), or even bare-metal programming |
| Development Model | Similar to PC/server development, applications run on top of the operating system | Typically firmware development based on RTOS, emphasizing timing and reliability | Mostly bare-metal or lightweight RTOS |
| Performance | Extremely high | High (but focuses on real-time performance rather than absolute peak computing power) | Low to medium (but with extremely high energy efficiency) |
| Power Consumption | High | Medium | Extremely low (many models support sleep modes, with power consumption as low as microamps) |
| Cost and Area | High (core complexity, usually requires external DRAM) | Medium | Extremely low (core simplicity, often integrated with Flash and SRAM as a single-chip MCU) |
4. Key Differences
4.1. Memory Management
4.1.1. MMU (Memory Management Unit)
MMU (<span>Memory Management Unit</span>) is the memory management unit, whose core function is virtual memory, which can map virtual addresses to physical addresses. This is a necessary condition for running a full operating system with features like process isolation and dynamic loading, such as Linux.
In addition to virtual memory, the MMU has the following features:
- Address Translation: The addresses seen by applications (virtual addresses) and the actual hardware addresses (physical addresses) are different. The MMU is responsible for translating virtual addresses into physical addresses in real-time. It’s like you only know the name of a department in a company (virtual address), and the receptionist (MMU) helps you find the specific room number of that department in the building (physical address).
- Memory Protection: It can set permissions for each memory page (e.g., read, write, execute). If a user program tries to write to the code area of the operating system (read-only), the MMU will trigger an exception (segmentation fault) to prevent illegal access.
- Process Isolation: Each process has its own independent virtual address space. Process A and Process B can use the same virtual address, but they will be mapped to different physical addresses by the MMU, thus completely isolating them from each other. This is the cornerstone of modern multitasking operating system stability.
- Demand Paging: Allows the operating system to use the hard disk as virtual memory (swap space), swapping out less frequently used memory pages to the hard disk when physical memory is insufficient, and swapping them back in when needed.
4.1.2. MPU (Memory Protection Unit)
MPU (<span>Memory Protection Unit</span>) is the memory protection unit that can only set access permissions for memory areas (e.g., read-only, no execution). It is simpler, has lower overhead, and is mainly used to protect critical code and data (for example, to prevent one task from accidentally overwriting another task’s data), thereby enhancing the system’s reliability and security. It cannot implement virtual memory, so it cannot run Linux.
4.1.3. Relationship Between the Two
- MMU is a superset of MPU. The MMU provides all the functions of the MPU (memory protection) and adds the crucial high-level function of virtual memory management.
- Relationship: You can think of the MPU as a stripped-down, lightweight version of the MMU. It is only responsible for “security” (protecting areas), while the MMU acts as both “security” and “high-level butler” (managing virtual address mapping).
4.2. Real-Time Performance
- Cortex-R and Cortex-M both emphasize real-time performance, but with different focuses.
- Cortex-R‘s “real-time” is hard real-time, meaning it must complete responses within a strictly defined deadline, or it will lead to catastrophic consequences (e.g., brake failure). Its entire design, from pipelining to memory access, is optimized for this.
- Cortex-M‘s real-time performance is usually soft real-time or in scenarios with less extreme hard real-time requirements. It can also respond quickly to interrupts, but its primary design goal is low power consumption and low cost.
4.3. Ecosystem and Development
- Cortex-A: Supports complex operating systems like Linux, Android, Windows. The development environment is complex (cross-compilation, kernel porting, driver development), leaning more towards traditional application software development.
- Cortex-M/R: Only supports real-time operating systems like RTOS. The development environment is relatively simple, commonly using IDEs (like Keil MDK, IAR Embedded Workbench, STM32CubeIDE) for firmware development, closer to hardware.
5. How to Check the Core Type of a Chip?
There are several methods to check the ARM core type used in a device (<span>Cortex-A</span>/<span>Cortex-R</span>/<span>Cortex-M</span>).
5.1. Software Query (The Simplest and Most Common)
5.1.1. Cortex-A Devices
Cortex-A devices typically run Linux or Android systems, and you can query them using the following methods.
1. Use the <span>lscpu</span> command
Enter this command in the terminal, and the output information is very detailed.
$ lscpu
Architecture: aarch64 # This indicates ARMv8-A 64-bit architecture
CPU(s): 8
On-line CPU(s) list: 0-7
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 2
Vendor ID: ARM
Model name: Cortex-A72 # This directly gives the core model!
Model: 3
...
2. Read the <span>/proc/cpuinfo</span> file
Enter <span>cat /proc/cpuinfo</span> in the terminal.
$ cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 4 (v7l) # Architecture and version
BogoMIPS : 38.40
Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm crc32
CPU implementer : 0x41
CPU architecture: 7** # '7' represents ARMv7
**CPU variant : 0x0
CPU part : 0xc07 # This code is key!
CPU revision : 4
...
3. How to Interpret the <span>CPU part</span>:
You need to compare the hexadecimal code of the <span>CPU part</span> (like <span>0xc07</span>) with the official ARM list.
| Part Num (Hex) | CPU Core Name | ARM Architecture Version | Typical Features and Application Notes |
|---|---|---|---|
| 0x920 | ARM920T | ARMv4T | With MMU, used in early smartphones, embedded devices |
| 0x922 | ARM922T | ARMv4T | Variant of ARM920T with different cache sizes |
| 0x926 | ARM926EJ-S | ARMv5TE | With Jazelle, MMU, widely used in feature phones, microcontrollers |
| 0x940 | ARM940T | ARMv4T | With MPU, used for real-time embedded applications |
| 0x946 | ARM946E-S | ARMv5TE | With MPU, configurable TCM, used in game consoles, embedded control |
| 0x966 | ARM966E-S | ARMv5TE | No cache, with TCM, used in deeply embedded applications |
| 0xb02 | ARM11 MPCore | ARMv6K | Supports 1-4 core SMP, used in smartphones, application processors |
| 0xb36 | ARM1136J(F)-S | ARMv6 | With SIMD, Jazelle, used in mobile devices |
| 0xb56 | ARM1156T2(F)-S | ARMv6T2 | With Thumb-2, MPU, used for real-time embedded applications |
| 0xb76 | ARM1176JZ(F)-S | ARMv6KZ | With TrustZone technology, used for secure application processors |
| 0xc05 | Cortex-A5 | ARMv7-A | High-performance application processor, supports multi-core |
| 0xc07 | Cortex-A7 | ARMv7-A | High-efficiency application processor, commonly used as a small core in big.LITTLE architectures |
| 0xc08 | Cortex-A8 | ARMv7-A | High-performance single-core application processor |
| 0xc09 | Cortex-A9 | ARMv7-A | High-performance multi-core application processor |
| 0xc0c | Cortex-A12 | ARMv7-A | Mid to high-end application processor |
| 0xc0f | Cortex-A15 | ARMv7-A | High-performance application processor, commonly used as a big core in big.LITTLE architectures |
| 0xc14 | Cortex-R4 | ARMv7-R | High-performance real-time processor |
| 0xc15 | Cortex-R5 | ARMv7-R | Real-time processor, supports dual-core lockstep |
| 0xc17 | Cortex-R7 | ARMv7-R | High-performance real-time processor |
| 0xc20 | Cortex-M0 | ARMv6-M | Ultra-low power microcontroller |
| 0xc21 | Cortex-M1 | ARMv6-M | Microcontroller designed for FPGA |
| 0xc23 | Cortex-M3 | ARMv7-M | High-performance microcontroller |
| 0xc24 | Cortex-M4 | ARMv7E-M | Microcontroller with DSP instructions |
| 0xc27 | Cortex-M7 | ARMv7E-M | High-performance microcontroller with DSP and FPU |
| 0xc60 | Cortex-M0+ | ARMv6-M | Ultra-efficient microcontroller |
| 0xd01 | Cortex-A32 | ARMv8-A | 32-bit only, high-efficiency application processor (AArch32) |
| 0xd03 | Cortex-A53 | ARMv8-A | High-efficiency 64-bit application processor, commonly used as a small core in big.LITTLE architectures |
| 0xd04 | Cortex-A35 | ARMv8-A | Extremely high-efficiency 64-bit application processor |
| 0xd05 | Cortex-A55 | ARMv8.2-A | High-efficiency AI-enhanced application processor (commonly found in mid-range smartphones) |
| 0xd07 | Cortex-A57 | ARMv8-A | High-performance 64-bit application processor, commonly used as a big core in big.LITTLE architectures |
| 0xd08 | Cortex-A72 | ARMv8-A | High-performance 64-bit application processor |
| 0xd09 | Cortex-A73 | ARMv8-A | High-performance, high-efficiency 64-bit application processor |
| 0xd0a | Cortex-A75 | ARMv8.2-A | High-performance 64-bit application processor |
| 0xd0b | Cortex-A76 | ARMv8.2-A | High-performance 64-bit application processor |
| 0xd0c | Cortex-A77 | ARMv8.2-A | High-performance 64-bit application processor |
| 0xd0d | Cortex-A78 | ARMv8.2-A | High-performance, high-efficiency 64-bit application processor |
| 0xd0e | Cortex-A710 | ARMv9-A | High-performance 64-bit application processor (ARMv9) |
| 0xd41 | Cortex-A78AE | ARMv8.2-A | Cortex-A78 version for automotive electronics |
| 0xd44 | Cortex-X1 | ARMv8.2-A | Extreme performance 64-bit application processor |
| 0xd4a | Cortex-A510 | ARMv9-A | High-efficiency small core (ARMv9) |
| 0xd4b | Cortex-A715 | ARMv9-A | High-performance, high-efficiency big core (ARMv9) |
| 0xd4c | Cortex-X2 | ARMv9-A | Extreme performance core (ARMv9) |
| 0xd4d | Cortex-A720 | ARMv9-A | (High-efficiency big core released in 2023) |
| 0xd4e | Cortex-X3 | ARMv9-A | (Extreme performance core released in 2023) |
| … | … (continuously updated) | … | … |
5.1.2. Cortex-R Devices
These processors are usually deeply embedded in dedicated devices (like hard disk controllers, automotive ABS systems) and do not provide user-accessible interfaces. Ordinary users can hardly query them directly, and can only do so by:
- Consulting the technical white paper or chip specifications.
- Inquiring with the device manufacturer.
5.1.3. Cortex-M Devices
Cortex-M devices (microcontrollers) typically do not have a general-purpose operating system, so they cannot run <span>lscpu</span><span>. The methods are as follows:</span>
- Check the chip model: This is the most direct method. The MCU chip will have its model printed on it, such as STM32F407VGT6.
- “ST” represents STMicroelectronics.
- “M32” represents the ARM Cortex-M core.
- “F4” represents the product series. F4 series typically uses the Cortex-M4 core.
- Consult the chip datasheet: This is the most authoritative method. Go to the chip manufacturer’s (like ST, NXP, Microchip, TI) official website to find the official datasheet for that model. It will clearly state whether it is Cortex-M0, M3, M4, M7, etc., in the introduction section.
- Identify through IDE: When you use IDEs like Keil, IAR, etc., to develop programs for the chip, the IDE will clearly list the core of that chip when selecting the device model.
6. Correspondence Between ARM Instruction Set Versions
6.1. Version Correspondence
This is a rough correspondence table that can help you understand their evolution.Note that an architecture version (like ARMv7) can derive profiles (A, R, M) suitable for different scenarios.
| ARM Architecture Version (ISA) | Release Focus | Cortex-A Application Processor | Cortex-R Real-time Processor | Cortex-M Microcontroller | Key Features |
|---|---|---|---|---|---|
| ARMv4 / v5 | Early Classics | ARM9, ARM11 | – | – | First introduced the Thumb instruction set |
| ARMv6 | Optimization and Expansion | – | – | Cortex-M0 / M0+ / M1 | Introduced Thumb-2, extremely high energy efficiency |
| ARMv7 | Profile Classification | Cortex-A5, A7, A8, A9, A15, A17 | Cortex-R4, R5, R7 | Cortex-M3, M4, M7 | NEON SIMD (A series), Thumb-2, hardware division |
| ARMv8 | 64-bit Revolution | Cortex-A53, A57, A72, A73, A75, A76, A77, A78, X1 | Cortex-R52, R82 | Cortex-M23, M33, M55, M85 | A64/ARM64 instruction set, TrustZone security extension |
| ARMv9 | Security and AI | Cortex-A710, A715, A510, X2, X3, X4 | – | (Future M series will follow) | SVE2 vector extension, confidential computing domain |
6.2. How to Understand This Table
-
Profile (Application Domain Segmentation): Starting from ARMv7, the architecture is clearly divided into three profiles:
- A-profile (Application): Used for high-performance application processors. The CPUs in our smartphones are basically ARMv7-A or ARMv8-A/ARMv9-A.
- R-profile (Real-time): Used for high real-time performance processors.
- M-profile (Microcontroller): Used for deeply embedded microcontrollers.
Backward Compatibility: The ARM architecture is backward compatible. For example, a processor that supports ARMv8-A (like Cortex-A53) can run 32-bit programs compiled for ARMv7-A.
Examples:
- If your
<span>lscpu</span>command shows<span>Model name: Cortex-A72</span>, then the instruction set architecture it uses is ARMv8-A. - If your chip model is STM32F103, consulting the datasheet reveals it is a Cortex-M3 core, then the instruction set architecture it uses is ARMv7-M.
- If your chip model is RP2040 (Raspberry Pi Pico), its core is Cortex-M0+, then the instruction set architecture it uses is ARMv6-M.