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1. Concepts of Synchronous and Asynchronous Exceptions
The following three behaviors are referred to as synchronous exceptions:
• The exception is generated as a result of direct execution or attempted execution of an instruction.
• The return address presented to the exception handler is guaranteed to indicate the instruction that caused the exception.
• The exception is precise.
In other words:
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The exception is generated by executing or attempting to execute an instruction.
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The location that generates the exception is determined, meaning every time execution reaches “that instruction”, the exception will occur.
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The exception is precise.
The following three behaviors are referred to as asynchronous exceptions:
• The exception is not generated as a result of direct execution or attempted execution of the instruction stream.
• The return address presented to the exception handler is not guaranteed to indicate the instruction that caused the exception.
• The exception is imprecise.
In other words:
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The exception is not generated by executing or attempting to execute an instruction.
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The location that generates the exception is not determined, meaning it is unknown where execution is at when the exception occurs.
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The exception is imprecise.
So what do precise and imprecise mean?
It’s a bit convoluted and hard to understand, let’s put it another way: an exception that occurs as expected is called precise, otherwise it’s imprecise.
2. What are the Synchronous Exceptions in the System?
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Any exception generated by attempting to execute an UNDEFINED instruction, including:
(1) Attempting to execute an instruction at an inappropriate exception level.
(2) Attempting to execute an instruction when the instruction is disabled.
(3) Attempting to execute an instruction bit pattern that has not been allocated.
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Illegal execution state exceptions. These are caused by attempting to execute an instruction when
<span>PSTATE</span><span>.</span><span>IL</span>is 1 (for details, refer to the illegal return events of AArch64 state on page D1-2486). -
Exceptions caused by using an unaligned SP.
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Exceptions caused by attempting to execute an instruction using an unaligned PC.
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Exceptions caused by instructions generated by exceptions SVC, HVC, or SMC.
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Exceptions caused by attempting to execute system registers defined to be captured at a higher exception level (for details, refer to configurable instruction enable and disable on page D1-2510).
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Exceptions associated with attempts to execute instructions from memory areas that have caused faults generated by the memory address translation system.
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Data aborts generated by the memory address translation system associated with attempts to read or write to memory that has caused faults.
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Data aborts caused by unaligned addresses.
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If implementing FEAT_MTE2, data aborts caused by tag check faults.
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All debugging exceptions: (1) Breakpoint Instruction exceptions. (2) Breakpoint exceptions. (3) Watchpoint exceptions. (4) Vector Catch exceptions. (5) Software Step exceptions.
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In implementations that support capturing floating-point exceptions, exceptions caused by captured IEEE floating-point exceptions.
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In some implementations, external aborts. External aborts are failed memory accesses, including those that occur during address translation.
3. Understanding SError
SError (also known as System Error) is a type of asynchronous exception, generally coming from <span>External</span><span>aborts</span>, which occurs when the bus generates an exception during memory system access. For example:
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When memory access is blocked by TZC, the bus returns an exception
Note that exceptions generated by MMU belong to <span>internal</span><span>abort</span>, which is a synchronous exception. Undefined instruction exceptions are also synchronous exceptions.
4. Understanding External Abort
External Abort can be a synchronous exception or an SError 
For example:
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Instruction Abort can be an internal synchronous exception or a synchronous External Abort.
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Data Abort can be an internal synchronous exception or a synchronous External Abort (meaning External Abort can belong to synchronous exceptions).
5. Instruction Abort and Data Abort
In the aarch64 architecture, instruction abort and data abort have become a type of synchronous exception. They are no longer a separate exception model. Therefore, when instruction abort or data abort occurs, it is definitely a synchronous exception, which may be an internal abort or an external abort, but ultimately it is a synchronous exception.
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