Detailed Process of Digital IC Design (ASIC Design)

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ASIC Design Process

1. Define Project Requirements

1. Determine the specific indicators of the chip:

• Physical Implementation

  Manufacturing process (foundry and process size);

  Die area (DIE size, affected by power consumption, cost, digital/analog area);

  Packaging (larger packaging results in better heat dissipation, but higher cost).

• Performance Indicators:

  Speed (clock frequency);

  Power consumption.

• Functional Indicators:

  Function description

  Interface definition

2. System-level design:

Use system modeling languages (high-level languages like Matlab, C, etc.) to describe each module to verify the feasibility of the solution.

2. Front-end Process

1. RTL Register Transfer Level Design

Use hardware description languages, such as Verilog, to describe the circuit based on the transfer between registers.

2. Functional Verification (Dynamic Verification):

Simulate and verify the functionality of the design, requiring stimulus driving; this is dynamic simulation. Verification tools include Mentor’s Modelsim, Synopsys’ VCS, and Cadence’s NC-Verilog, which can be used to verify RTL-level code. This part is called pre-simulation, and after logic synthesis, another simulation can be referred to as post-simulation.

3. Logic Synthesis (Design Compile):

Specific synthesis libraries need to be specified, and constraint files added; logic synthesis generates the gate-level netlist (Netlist).

4. Formal Verification (Static Verification):

Verify functionality using the synthesized netlist. Commonly used methods include equivalence checking, comparing the functionality of the synthesized netlist against the HDL design after functional verification, ensuring that the original circuit functionality of the HDL description has not changed during the logic synthesis process. Synopsys’ Formality tool is used for equivalence checking.

5. STA Static Timing Analysis:

Analyze timing using Synopsys’ PT (Prime Time) tool, usually used in back-end design, where layout-generated netlists provide more accurate STA;

STA meets timing constraints, resulting in the final Netlist.

6. DFT (Design for Test) Design for Testability:

To test the chip’s yield after production and check for defects, a scan chain is typically inserted into the circuit;

DFT is performed after obtaining the Netlist and before layout and routing (Place and Route).

3. Back-end Process

1. Layout and Routing (Place and Route):

Includes clock tree insertion (layout clock lines), layout and routing using Synopsys’ IC Compiler (ICC) tool.

Before routing (ordinary signal lines), layout the clock lines, which is clock tree synthesis (CTS), using Synopsys’ Physical Compiler tool.

2. Parasitic Parameter Extraction (Extract RC):

Extract delay information

3. Static Timing Analysis (STA):

Includes layout and routing delays for more realistic timing analysis

4. Layout Physical Verification:

DRC (Design Rule Check), LVS (Layout Versus Schematic)

Tools:

Mentor: Calibre

Synopsys: Hercules

Cadence: Diva/Dracula

5. Generate GDSII files, Tap-off for tape-out

(Note: The entire IC design process is iterative; if any step does not meet requirements, the previous process must be repeated until the requirements are met before proceeding to the next step.)

IC Design Process Terminology Overview (Including EDA Tools for Each Process)

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The job content, recruitment requirements, and development prospects vary for different directions. Once a direction is chosen, it can be relatively troublesome to change jobs later. So how can one determine the employment direction from the beginning?