Overview of Exception Masking

In the x86 architecture, the Floating Point Unit (FPU) provides a set of exception handling mechanisms. By default, all floating-point exceptions are masked, which means that when an exception occurs, the processor provides a default result and continues execution without interrupting the program flow.

FPU Control Word Structure

The FPU control word is a 16-bit register that controls the behavior of floating-point operations:

Bit  Function                Bit  Function
0   Invalid Operation Exception Mask     5   Precision Exception Mask
1   Denormal Operand Exception Mask    8-9 Precision Control Bits
2   Divide by Zero Exception Mask       10-11 Rounding Control Bits
3   Overflow Exception Mask             12  Infinity Control Bit
4   Underflow Exception Mask

Code Example

Divide by Zero Operation in Default Masked State

.data
val1 DWORD 1
val2 REAL8 0.0
result REAL8 ?

.code
; In the default state, exceptions are masked, and divide by zero results in infinity without interrupting the program
fild val1        ; Load integer 1 into ST(0)
fdiv val2        ; ST(0) = positive infinity
fstp result      ; Store result

Unmasked Divide by Zero Exception

.data
ctrlWord WORD ?
val1 DWORD 1
val2 REAL8 0.0

.code
; Step 1: Get the current control word
fstcw ctrlWord

; Step 2: Clear bit 2 (divide by zero exception mask bit)
and ctrlWord, 1111111111111011b

; Step 3: Load the modified control word back to FPU
fldcw ctrlWord

; Now executing divide by zero will trigger an exception
fild val1
fdiv val2        ; Trigger divide by zero exception
fst val2         ; This instruction will display an error message

Masking Divide by Zero Exception

.data
ctrlWord WORD ?

.code
; Mask divide by zero exception
fstcw ctrlWord       ; Get control word
or ctrlWord, 100b    ; Set bit 2 (mask divide by zero exception)
fldcw ctrlWord       ; Load result back to FPU

Overview of Mixed Mode Operations

x86 assembly supports mixed operations with different data types:

.data
intVal DWORD 10
realVal REAL8 3.14

.code
; Mixed operations between integer and floating-point
fild intVal      ; Load integer to floating-point stack
fld realVal      ; Load floating-point number
fadd             ; ST(1) + ST(0), result stored in ST(0)

Overview of x86 Instruction Encoding

x86 instructions use a variable-length encoding format:

[Prefix] [Opcode] [ModR/M] [SIB] [Displacement] [Immediate]

Example:

; Instruction: ADD EAX, 42h
; Encoding: 83 C0 42
; 83 - Opcode
; C0 - ModR/M byte (EAX register)
; 42 - Immediate value

Summary of Exception Types

Exception Type	Default Behavior When Masked	Behavior When Unmasked
Invalid Operation	Returns QNaN	Triggers exception handler
Divide by Zero	Returns infinity	Triggers exception handler
Overflow	Returns maximum finite value	Triggers exception handler
Underflow	Returns denormal number	Triggers exception handler
Precision	Returns rounded result	Triggers exception handler

Practical Application Recommendations

1. Development Phase: It is recommended to unmask exceptions to detect errors promptly
2. Production Environment: Exceptions are usually masked to ensure program stability
3. Critical Calculations: Enable precision exception detection in critical sections
4. Performance Considerations: Exception handling incurs overhead, requiring careful consideration

This exception handling mechanism allows developers to flexibly control the strictness of floating-point operations based on specific needs.