Source: EETOP BBS Author: leishangwen (Community Moderator)
Recently, Wave officially announced that it will grant free licenses for the MIPS Instruction Set Architecture (ISA) to global customers. This initiative provides free access to the MIPS architecture for semiconductor companies, developers, and universities worldwide, enabling them to develop the next generation of System on Chip (SoC). The MIPS architecture opening plan will provide all participants with the latest 32-bit and 64-bit MIPS architectures at no cost for architecture licensing and copyright fees, while also offering protection for hundreds of existing patents globally for all users of the MIPS architecture.
Although this move will not have much immediate impact on the well-established X86 and ARM architectures, it poses a significant challenge to RISC-V, which has been attracting players with its open-source banner. The reason many manufacturers are enthusiastic about RISC-V is that any IC design unit globally can design CPUs based on RISC-V without any intellectual property issues. This makes IC design companies very interested in RISC-V.
However, with MIPS also announcing free licensing, the advantages that were previously unique to RISC-V are now shared with MIPS, allowing everyone to design CPUs based on MIPS. It can be said that after the free licensing of the MIPS instruction set, due to a more complete ecosystem and better performance, it will greatly impact RISC-V.
Of course, MIPS cores are not open source, and core licensing remains intact. This is a very rational business arrangement, expanding the entire instruction set ecosystem through the open-source instruction set, and then using the expanded ecosystem to feed back into the core licensing business, completing a complete commercial closed loop.
A few years ago, EETOP established the OpenMIPS community, where the moderator shared a relatively advanced MIPS design and code. However, at that time, MIPS was not open, so it could only be labeled as a learning or educational version.
Community Screenshot
The moderator has shared the development notes and implementation code for designing a MIPS CPU in 10 days in the community, which is now introduced to everyone for learning.
Development Notes
To thank all the students on EETOP and moderator tyxuanyuanlx for their support of the book “Step by Step into the Core – Internal Design Analysis of Soft Core Processors”, I will contribute an open-source processor called OpenMIPS.
OpenMIPS is a 32-bit scalar processor with a Harvard architecture, compatible with the MIPS32 architecture, allowing it to use existing MIPS compilation environments. OpenMIPS has the following features:
(1) Five-stage integer pipeline: instruction fetch, decode, execute, memory access, write back. (2) Harvard architecture with separate instruction and data interfaces. (3) 32 32-bit integer registers. (4) Big-endian mode. (5) Vectorized exception handling with precise exception handling support. (6) 8 external interrupts. (7) 32-bit data and address bus width. (8) Single-cycle multiplication. (9) Supports delayed branching. (10) Compatible with MIPS32 architecture, supporting all integer instructions in the MIPS32 instruction set. (11) Most instructions can be completed in one clock cycle. (12) Synthesizable. I plan to release it sequentially over ten days, hence the title “10 Days to Implement a Processor – OpenMIPS Development Notes”. I hope everyone will use it extensively and provide suggestions for improvement. The rough plan is as follows: Day 1
(1) Introduction to OpenMIPS.
(2) Setting up the experimental environment.
(3) Implementing the general register Regfile.
(4) Implementing the instruction memory imem.
(5) Implementing the data memory dmem.
Day 2
(1) Implementing the five-stage pipeline framework.
(2) Implementing the first instruction – ORI.
Day 3
(1) Resolving pipeline data hazards.
(2) Implementing the remaining logical operation instructions – AND, ANDI, LUI, NOR, OR, XOR, XORI.
Day 4
(1) Implementing shift operation instructions – SLL, SLLV, SRA, SRAV, SRL, SRLV.
(2) Implementing all arithmetic operation instructions except multiplication and division – ADD, ADDI, ADDIU, ADDU, CLO, CLZ, SLT, SLTI, SLTIU, SLTU, SUB, SUBU.
Day 5
(1) Implementing multiplication instructions – MADD, MADDU, MSUB, MSUBU, MUL, MULT, MULTU.
(2) Implementing division instructions – DIV, DIVU.
Day 6
(1) Implementing move operation instructions – MFHI, MFLO, MOVN, MOVZ, MTHI, MTLO.
(2) Implementing control instructions – NOP, SSNOP.
Day 7
(1) Implementing jump instructions – J, JAL, JALR, JR.
(2) Implementing branch instructions – B, BAL, BEQ, BGEZ, BGEZAL, BGTZ, BLEZ, BLTZ, BLTZAL, BNE.
Day 8
(1) Implementing load instructions – LB, LBU, LH, LHU, LL, LW, LWL, LWR.
(2) Implementing store instructions – SB, SC, SH, SW, SWL, SWR.
Day 9
(1) Implementing some registers of coprocessor CP0.
(2) Implementing coprocessor access instructions – MFC0, MTC0.
Day 10
(1) Implementing trap instructions – SYSCALL, TEQ, TEQI, TGE, TGEI, TGEIU, TGEU, TLT, TLTI, TLTIU, TLTU, TNE, TNEI.
(2) Implementing interrupt handling.
(3) Implementing exception return instructions – ERET.
Here we only provided an overview of what needs to be done each day; all these detailed designs have already been uploaded by the moderator as attachments in the corresponding forum posts, and everyone can click to read the original text at the end to download.
Code Implementation Explanation
Compared to the OpenMIPS educational version, the biggest feature of the OpenMIPS practical version is the introduction of the Wishbone bus interface, forming a SOPC that includes an SDRAM controller, GPIO controller, flash controller, UART controller, and has been tested on the DE2 board. The structure of the SOPC is as follows:
The directory structure is as follows:(The code includes Verilog and VHDL, here we take VHDL as an example)
Each folder is explained as follows:rtl All source code files for the OpenMIPS practical version are in this folder, including pipeline file iu.vhd, division module div.vhd, register file Regfile.vhd, top-level file OpenMIPS.vhd, macro definition file stdlib.vhd.
min_sopcIncludes various IP cores: GPIO, UART, SDRAM controller, flash controller, Wishbone bus interconnect matrix, etc., as well as a top-level file OpenMIPS_min_sopc.vhd used to test OpenMIPS, in which the above IP cores are instantiated and connected to OpenMIPS through the Wishbone bus interconnect matrix, forming a SOPC. The structure of this SOPC will be introduced in section 8. All IP cores here are downloaded from OpenCores and comply with the Wishbone bus interface specifications.
toolsContains some tools related to specific evaluation boards. The author mainly uses Altera’s DE2 as the evaluation board, so there is a directory for Altera/DE2 under tools, which contains the DE2_control_panel software that can read and write the flash chip on DE2. This directory also includes a BinMerge.exe software, which will be useful in experiments with BootLoader and SimpleOS for merging binary files generated by BootLoader and SimpleOS.
docContains some documentation, specifically: “MIPS32 Instruction Set”, “MIPS Architecture for Programmers Volume III”, “OpenMIPS Quick Start Manual (Practical Version)”, “10 Days to Implement a Processor – OpenMIPS Growth Record”, as well as manuals for various IP cores in the min_sopc folder.asm_testContains several test programs, all written in assembly, used to test GPIO, UART, SDRAM, and a comprehensive program. This comprehensive program consists of BootLoader and SimpleOS, simulating the startup of an operating system.
OpenMips CPU Module Connection Diagram
Click to read the original text to enter the community and download the source code
