Overview of Common Communication Methods Between Microcontrollers
1. Asynchronous Serial Communication Using Hardware UART. This is a communication method that occupies fewer pins, is effective, and reliable; however, many small microcontrollers lack hardware UART, and some only have one UART. If the system also needs to communicate with a host computer, the hardware resources are insufficient. This method is generally used when the microcontroller has hardware UART and does not need to communicate serially with the outside world or in cases where dual UART microcontrollers are used.
2. Serial Communication Using On-Chip SPI Interface or I2C Bus Module. The SPI/I2C interface features simple hardware and easy software programming, but currently, most microcontrollers do not have hardware SPI/I2C modules.
3. Software Emulation of SPI/I2C Communication, this method is difficult to simulate the slave mode, both parties must respond to each bit, and the communication speed and software resource overhead can create a significant conflict, which, if not handled well, can lead to a sharp decline in overall system performance. This method can only be used in scenarios with very little communication volume.
4. Point-to-Point Parallel Communication, Directly Connecting Microcontroller Pins with 1-2 Handshake Signal Lines. This method is characterized by fast communication speed, allowing the transmission of 4 bits or 8 bits at a time, or even more, but it requires a large number of pins, and the data transfer is quasi-synchronous. After one microcontroller transmits one byte to another, it must wait for the receiving acknowledgment signal from the other microcontroller before transmitting the next data. This is generally used in scenarios where there are ample hardware pins available.
5. Communication Using Dual-Port RAM as a Buffer. The main feature of this method is its fast communication speed, as both sides can directly operate using read/write memory instructions; however, this method requires a large number of pins, and dual-port RAM is very expensive, typically only used in scenarios with special speed requirements.
From the above methods, it can be seen that each method has significant hardware requirements and limitations, especially difficult to implement on functionally simple microcontrollers. Therefore, seeking a simple and effective method for communication between various microcontrollers is of great significance. In methods ③ and ④, both microcontrollers must respond to each bit or byte transmitted, which consumes a lot of software resources when the communication data volume is large, which is not acceptable in high real-time requirement scenarios.
To address this issue, suppose we add a data buffer between the microcontrollers, allowing a large amount of data to be written into the buffer first, and then letting the other party retrieve it. Each microcontroller operates in a master mode with respect to the data buffer, which will greatly improve communication efficiency. When we talk about data buffering, we immediately think of parallel RAM, but parallel RAM requires a large number of pins (data lines + address lines + read/write lines + chip select lines + handshake lines), generally more than 16. This is a daunting number and will significantly increase PCB area and complicate wiring, making it rarely adopted. Serial interface RAM is rarely seen in the market, not only is it hard to find but also very expensive. Shift registers can also serve as data buffers, but currently, the largest capacity is only 128 bits, and due to the “first in, first out” structure, regardless of how much data is transmitted, the receiver must shift the entire register, which is inflexible and large-capacity shift registers are also rare and hard to find. The emergence of a chip known as “ferroelectric memory” provides us with a solution.
Using Ferroelectric Memory as a Data Buffer for Communication
Ferroelectric memory is a non-volatile memory device introduced by Ramtran in the USA, abbreviated as FRAM. Compared to ordinary EEPROM and Flash-ROM, it has the advantages of no write time, unlimited read/write cycles, and no distribution structure for continuous writing, thus possessing the dual characteristics of RAM and EEPROM, and is relatively inexpensive.
Currently, most microcontroller systems are equipped with serial EEPROM (such as 24CXX, 93CXX, etc.) for parameter storage. If one FRAM chip replaces the existing EEPROM, it can store parameters and serve as a buffer for serial data communication. Two (or more) microcontrollers can connect to one FRAM in a multi-master-slave I2C bus configuration, adding a few handshake lines to achieve a simple and efficient communication hardware circuit. In terms of software, as long as the control conflict and communication protocol issues of the I2C multi-master-slave are resolved, simple, efficient, and reliable communication can be achieved.
Example (Dual Microcontroller Structure, Multi-Function Low-Power System)
(1) Hardware
The W78LE52 and EMC78P458 form a battery-powered industrial flow meter capable of remote communication. The 78P458 uses a 32.768kHz crystal oscillator, has low operating current, continuous operation, and real-time collection of sensor pulses and analog quantities such as temperature and pressure; the W78LE52 uses an 11.0592MHz crystal oscillator, and due to its higher operating current, it operates intermittently, responsible for nonlinear flow correction, parameter input, LCD display, and communication with the host computer, with its UART used for remote communication. The two microcontrollers share one I2C interface FRAM (FM24CL16) in a two-master-one-slave I2C bus control mode, with W78LE52’s P3.5 and P3.2 connected to 78P458’s P51 and P50 as handshake signal lines A and B. We define handshake line A (referred to as line A) as the bus control and indication line, mainly used to obtain bus control and determine whether the bus is “busy”; handshake line B (referred to as line B) is defined as the notification line, mainly used to notify the other party to retrieve data.
(2) I2C Bus Arbitration
Since we are using a two-master-one-slave I2C bus configuration, preventing two masters from simultaneously operating the slave (conflict prevention) is a very important issue. Devices with hardware I2C modules generally have an internal bus arbiter and a bus timeout timer: when the bus timeout timer times out, it indicates that the bus is idle, at which point the microcontroller can issue a bus acquisition command. The bus arbiter confirms the success or failure of the bus acquisition through a series of operations; the timeout timer is reset, and every subsequent SCL state change resets the timeout timer for all master devices to prevent overflow, indicating that the bus is in a “busy” state until one master ends control of the bus and no longer generates SCL pulses; if the timeout timer overflows, the bus returns to the “idle” state. However, currently, most microcontrollers do not come equipped with hardware I2C modules, and when the working frequencies of the two masters differ significantly, the timeout timer’s timing value can only be set to a larger value, which also affects the bus’s usage efficiency.
Below is a method for software simulating I2C bus arbitration (software simulation of I2C read/write operations is quite common, and will not be elaborated here): using one handshake line A, when line A is high, it indicates that the bus is idle; when one master wants to acquire bus control, it first checks if the bus is idle, if “busy” it exits, if idle, it sends a test sequence (e.g., 1000101011001011) to line A, reading the state of line A after each bit “1” is sent. If the read state is “0”, it exits immediately, indicating that another device has already acquired the bus; if the state of line A is correct for the entire sequence read, it indicates that the bus control has been successfully obtained, at which point it pulls line A low to indicate that the bus is “busy” until the read/write high line A releases the bus back to the “idle” state. Different masters can use different test sequences or generate random test sequences, and the length of the test sequence can be chosen to be longer to increase the reliability of arbitration.
(3) Communication Protocol
A reliable communication system, in addition to good hardware circuits, also requires a crucial communication protocol. In microcontroller systems where RAM resources and execution speed are very limited, a simple and effective protocol is very important. Below is a specific introduction to a protocol that is quite suitable for microcontroller communication, where data is transmitted in packets. Packet structure:
① Header – indicates the start of the data packet, beneficial for packet integrity checking, sometimes can be omitted;
② Address – the target address for the data packet to be transmitted, can be omitted if only dual-machine communication or hardware distinguishes addresses;
③ Packet Length – indicates the length of the entire data packet;
④ Command – indicates the function of this data packet;
⑤ Parameters – the data and parameters to be transmitted;
⑥ Checksum – verifies the correctness of the data packet, which can be a sum check, XOR check, CRC check, or a combination of them;
⑦ Footer – indicates the end of the data packet, beneficial for packet integrity checking, sometimes can be omitted.
(4) Communication Process
First, the FRAM should be divided into various areas, including parameter areas and data reception areas for each microcontroller. Then, a microcontroller can send a data packet to another microcontroller, and after sending, it sends a pulse to handshake line B to notify the other party to retrieve the data; the receiving party reads the data and processes it, then writes back data or a communication failure flag to the sender’s data reception area in FRAM, and then sends a pulse to handshake line B in response to the sender.
If microcontroller 2 needs to send, the operation process can simply be reversed.
Conclusion
Through practice, it can be seen that the above methods are feasible. Compared to other methods, they have the following advantages:
① Simple. Occupies fewer microcontroller pins (SCL, SDA, handshake line A, handshake line B).
② Universal. Software simulation of I2C master mode can communicate between any type of microcontroller.
③ Efficient. Due to the use of data buffering, communication can occur between microcontrollers with different clock frequencies and speeds; during read/write operations, data can be transmitted at the highest speed of the I2C bus, allowing for large amounts of data to be transmitted at once; when one microcontroller transmits data to FRAM, the other microcontroller does not need to respond one by one or wait, allowing it to perform other program operations, improving software work efficiency.
④ Flexible. The communication hardware interface is equal for each microcontroller, and through software configuration, each microcontroller can actively send communication as needed or only respond to calls from other microcontrollers.
⑤ Easy to Expand. By adding address recognition lines and modifying the communication protocol, multi-machine communication can be achieved.
Points to Note:
① To improve communication efficiency, it is best to use interrupt ports for handshake line B, and the negative pulse width must meet the interrupt signal requirements of the slower microcontroller. If there is no interrupt, an additional pin should be added to notify the other party by changing the port state, waiting for the other party to query, rather than using a negative pulse.
② When sending a negative pulse to the other party, one should mask their own interrupts.
③ Since parameters and communication buffers are set in the same FRAM, care must be taken to avoid erroneous operations on the parameter section. A good solution is to store parameters in the latter half of the address (A2=1), and during communication operations, pull the FRAM’s WP pin high (write protection for the address in the latter half), which can effectively prevent erroneous operations on the parameter area during testing.
④ Since the I2C bus only allows one master and one slave at a time, when one microcontroller is writing communication data, the other microcontroller cannot operate on FRAM. If real-time, frequent reading of parameters from FRAM is required, please pre-load the parameters into RAM for use or add a dedicated chip for storing parameters.
-END-
﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌﹌
Disclaimer:This article is reprinted from the internet, and the copyright belongs to the original author. If there are any copyright issues, please contact us in a timely manner, thank you!
Collection of Previous Excellent Articles
Discussing the Formation Control Methods of Drones.Click here>>
Essentials | Implementing Gesture Recognition with Stereo Cameras, Perfectly Reproducing Human Motion Gestures.Click here>>After this article, do not ask me how to make a smart car.Click here>>//endIf you find the article good,share it, it is also our motivation to continue updating.5T Resource Giveaway! Including but not limited to: C/C++, Linux, Python, Java, PHP, Artificial Intelligence, PCB, FPGA, DSP, LabVIEW, Microcontrollers, etc.!Reply “More Resources” in the public account to get it for free, looking forward to your attention~
Long press to recognize the QR code in the image to follow