1. TTL Levels:
TTL level signals are most commonly used because data representation typically follows binary rules, where +5V is equivalent to logic ‘1’ and 0V is equivalent to logic ‘0’. This is known as the TTL (Transistor-Transistor Logic) signal system, which is the standard technology for communication between various components within devices controlled by computer processors.
TTL level signals are ideal for data transmission within devices controlled by computer processors. Firstly, the data transmission within these devices does not require high power and has low thermal losses. Moreover, TTL level signals connect directly to integrated circuits without the need for expensive line drivers and receiver circuits. Furthermore, data transmission within devices controlled by computer processors occurs at high speeds, and the TTL interface operations can meet this requirement. TTL communication is mostly conducted using parallel data transmission, which is not suitable for distances exceeding 10 feet due to reliability and cost reasons. This is because there are issues of skew and asymmetry in parallel interfaces that affect reliability.
TTL output high level >2.4V, output low level <0.4V. At room temperature, the general output high level is 3.5V and the output low level is 0.2V. Minimum input high level and low level: input high level >=2.0V, input low level <=0.8V, noise margin is 0.4V.
TTL circuits are current-controlled devices; they are fast with short transmission delays (5-10ns), but have high power consumption.
Output L: <0.8V; H: >2.4V.
Input L: <1.2V; H: >2.0V
TTL devices output low level must be less than 0.8V and high level must be greater than 2.4V. For input, below 1.2V is considered 0, and above 2.0V is considered 1.
2. CMOS Levels:
Output L: <0.1*Vcc; H: >0.9*Vcc.
Input L: <0.3*Vcc; H: >0.7*Vcc.
For a CMOS power supply of 12V, input below 3.6V is low level, with a noise margin of 1.8V; above 3.5V is high level, with a noise margin of 1.8V. This provides a higher noise margin than TTL.
3. RS232 Standard
Logic level 1 is -3 to -15V, and logic level 0 is +3 to +15V. Note that the level definitions are inverted.
Differences Between TTL and CMOS Levels
1. The definitions of the upper and lower limits differ; CMOS has a larger noise immunity area. When powered at 5 volts, TTL is generally around 1.7V and 3.5V, while CMOS is generally around 2.2V and 2.9V. These values are not precise and are for reference only.
2. The current driving capabilities differ; TTL generally provides a driving capability of 25mA, while CMOS is around 10mA.
3. The required input current size also differs; TTL generally requires around 2.5mA, while CMOS requires almost no input current.
4. Many devices are compatible with both TTL and CMOS, as indicated in the datasheet. If speed and performance are not considered, devices can generally be interchanged. However, it should be noted that sometimes load effects may cause the circuit to malfunction, as some TTL circuits require the input impedance of the next stage as a load to function properly.
1. Logic Levels of TTL and CMOS Circuits
VOH: Output voltage for logic level 1
VOL: Output voltage for logic level 0
VIH: Input voltage for logic level 1
VIL: Input voltage for logic level 0
Critical values for TTL circuits:
VOHmin = 2.4V VOLmax = 0.4V
VIHmin = 2.0V VILmax = 0.8V
Critical values for CMOS circuits (with a power supply voltage of +5V)
VOHmin = 4.99V VOLmax = 0.01V
VIHmin = 3.5V VILmax = 1.5V
2. Logic Level Conversion Between TTL and CMOS
CMOS levels can drive TTL levels.
TTL levels cannot drive CMOS levels without a pull-up resistor.
3. Characteristics of Common Logic Chips
74LS Series: TTL Input: TTL Output: TTL
74HC Series: CMOS Input: CMOS Output: CMOS
74HCT Series: CMOS Input: TTL Output: CMOS
CD4000 Series: CMOS Input: CMOS Output: CMOS
