In microcontrollers, the STM32F103 is powerful and widely used. To ensure the stable operation and performance optimization of the STM32F103 system, configuring its clock system is essential. So, how do we configure it?
1. Clock Source Selection
HSI: Internal RC oscillator with a frequency of 8MHz, suitable for situations where clock frequency accuracy is not critical or for smaller products.
HSE: External crystal oscillator, usually at a speed of 8MHz, provided by external circuits, offering higher accuracy and stability.
LSI: Internal RC oscillator with a frequency of 40kHz, mainly used for low-speed peripherals like watchdog timers.
LSE: External crystal oscillator with a frequency of 32.768kHz, mainly used for low-speed peripherals like RTC (Real-Time Clock).
2. System Clock Settings
① Select Clock Source
SYSCLK can choose HSI, HSE, or PLLCLK as the clock source. Among these, PLLCLK is the clock signal after frequency multiplication through the Phase-Locked Loop (PLL), providing higher clock frequencies.
If HSI is chosen as the clock source, the maximum system clock frequency is 64MHz (HSI/2*16).
If HSE is chosen as the clock source, the maximum system clock frequency is 72MHz (HSE multiplied by the PLL multiplication factor).
② Set Clock Frequency
By configuring the relevant bits in the Clock Configuration Register (CFGR), the system clock frequency can be set. For example, choosing HSE as the clock source and multiplying through PLL to 72MHz requires configuring the input clock source and multiplication factor for PLL.
3. Peripheral Clock Configuration
AHB bus clock (HCLK): Obtained by dividing the system clock SYSCLK, usually not divided to maintain maximum clock frequency.
APB1 bus clock (PCLK1): Obtained by dividing HCLK, with a maximum frequency of 36MHz. Peripherals on the APB1 bus include watchdog timers, timers, RTC, USART, etc.
APB2 bus clock (PCLK2): Obtained by dividing HCLK, but usually not divided to maintain the same frequency as HCLK. Peripherals on the APB2 bus include ADC, DAC, SPI, I2C, etc.
4. Specific Configuration Steps
Turn on the external high-speed clock HSE and wait for it to stabilize.
Configure PLL clock source and multiplication factor, enable PLL, and wait for it to be ready.
Set the division factor of the AHB bus clock HCLK (usually not divided).
Set the division factor of the APB1 bus clock PCLK1 (e.g., 2 division to get 36MHz).
Set the division factor of the APB2 bus clock PCLK2 (usually not divided).
Select PLLCLK as the clock source for the system clock SYSCLK.
Verify whether the system clock is set correctly.
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