Bus – SerDes

SerDes BusThis is a very important technology, but the name may sound a bit technical. I will explain it as clearly as possible.

1. Core Concepts: What is SerDes?

SerDes is a combination of Serializer and Deserializer.

It is an integrated circuit or functional module used for high-speed serial communication.

• Serializer: Located at the transmitting end. Its responsibility is to convert wide parallel data (e.g., 16bit, 32bit, 64bit) into a high-speed serial data stream one bit at a time.

• Deserializer: Located at the receiving end. Its responsibility is the opposite of the serializer, converting the received high-speed serial data stream back to the original parallel data.

A common misconception: SerDes itself is not a “bus protocol” like I2C or SPI, but a physical layer (PHY) technology. It is the underlying engine for implementing various high-speed bus protocols. You can think of it as the engine of a car, while various protocols (such as PCIe, SATA) are different models of cars.

2. Why is SerDes needed? – Addressing the “Parallel Bus Bottleneck”

In the early days, computers primarily used parallel buses (such as PCI, ATA, DDR) to transmit data. The data width could be 32bit or 64bit, with each bit having a separate physical line. As data rates continued to increase (in the GHz range), parallel buses encountered several critical bottlenecks:

1.Timing synchronization (clock skew) issues:

• At extremely high frequencies, even slight differences in length and capacitance/inductance between parallel signal lines can cause data bits to arrive at the receiving end at different times. Some bits arrive faster, while others are slower, making it difficult for the receiver to sample all data correctly at the right moment, leading to errors. It’s like a group of soldiers, where the fast runners and slow runners cannot reach the finish line simultaneously.

2.Signal integrity (interference) issues:

• A large number of parallel data lines closely arranged can cause severe crosstalk and electromagnetic interference (EMI).

3.PCB routing and pin costs:

• Parallel buses require a large number of pins and PCB traces, which occupy significant chip area and board space, leading to high costs.

SerDes solutions::

• Converting parallel to serial: Merging multiple low-speed parallel channels into a single ultra-high-speed serial channel fundamentally eliminates timing skew issues between data bits.

• Reducing connections: Only a minimal number of high-speed differential signal pairs (usually one pair for transmission and one pair for reception) and a few control lines are needed, greatly simplifying routing, reducing pin costs, and crosstalk.

• Differential signal transmission: SerDes typically uses low-voltage differential signaling (LVDS) technology, which transmits a signal using two wires (positive and negative), providing strong common-mode noise rejection and significantly improving signal integrity and transmission distance.

3. Working principles and key technologies of SerDes

A typical SerDes system includes the following key components and processes:

1.Basic process:

• Transmitter (TX): Parallel data -> Serializer -> Encoder -> Driver -> Sent through differential pairs.

• Receiver (RX): Received from differential pairs -> Equalizer -> Clock data recovery -> Decoder -> Deserializer -> Parallel data.

2.Core technologies:

• Encoding/Decoding: Common encoding methods include 8b/10b or 64b/66b.

• Purpose: To ensure that there are enough level transitions (0->1, 1->0) in the transmitted data so that the receiver can reliably recover the clock signal; while also achieving DC balance (approximately equal numbers of 0s and 1s), and embedding control characters (such as frame start, frame end).

• Clock Data Recovery (CDR)::

• This is the core magic of SerDes. In a serial link, there is no separate clock line.

• CDR circuits monitor the transition edges of the input data stream, using techniques such as phase-locked loops (PLLs) to “extract” a clock signal synchronized with the transmitter from the data itself, and then use this clock to accurately sample the data.

• Equalization::

• High-speed signals can experience distortion during transmission due to channel loss (from PCB materials, connectors), (high-frequency components attenuate, pulse widening, i.e., “inter-symbol interference”).

• Pre-emphasis at the transmitter or de-emphasis and the receiver’s equalizer will actively enhance high-frequency components or compensate for high-frequency losses, thus “flattening” the frequency response curve and reopening the eye diagram.

4. Application areas of SerDes

Almost all modern high-speed communication standards are based on SerDes technology, such as:

• Inside computers:

• PCI Express (PCIe): Buses for communication between graphics cards, SSDs, network cards, and CPUs.

• SATA / SAS: Connecting hard drives and solid-state drives.

• Network communication:

• Ethernet (Ethernet): Gigabit (1G), 10 Gigabit (10G), and higher-speed Ethernet PHYs.

• Fibre Channel (Fibre Channel): Used for storage area networks (SAN).

• Inter-chip interconnect:

• Serial RapidIO, JESD204 (for high-speed ADC/DAC), CPRI (for wireless base stations).

• Display interfaces:

• DisplayPort, HDMI: Higher versions of display interfaces also use serial transmission based on SerDes.

5. Advantages and challenges of SerDes

Advantages:

• High speed: Easily achieves single-channel rates from Gbps to tens of Gbps.

• Low pin count: Simplifies chip design and packaging.

• Strong anti-interference capability: Differential signaling and encoding techniques provide excellent signal integrity.

• Long transmission distance: Compared to parallel buses, it can transmit over longer distances through backplanes and cables.

• Good scalability: Bandwidth can be easily expanded by increasing the number of lanes (e.g., PCIe x1, x4, x16).

Challenges:

• Complex design: The design of CDR, equalizers, and other analog/mixed-signal circuits is extremely challenging, representing a technical barrier for high-end chips.

• High testing costs: Expensive equipment (such as high-speed oscilloscopes) is required for eye diagrams, jitter, and other tests.

• Power consumption: High-speed circuits typically consume more power.

Conclusion:

Characteristics	Traditional Parallel Bus	SerDes (High-Speed Serial Bus)
Data form	Multiple parallel	Single serial
Clock	Separate clock line	Embedded clock (recovered via CDR)
Signal type	Single-ended signal	Differential signal (LVDS)
Pin count	Many (data lines + clock line + control lines)	Very few (1 pair of TX differential lines + 1 pair of RX differential lines)
Rate/Bandwidth	Lower, limited by timing skew	Very high, up to tens of Gbps per channel
Anti-interference capability	Weak	Strong
PCB routing	Complex, many equal-length lines	Simple, fewer traces

In simple terms, SerDes is the technology that transforms low-speed, wide “multi-lane provincial roads” into high-speed, precise “single-lane super highways”, serving as the cornerstone for modern computing and communication systems to achieve high performance.