Analysis of MIPI DSI Display Case

The SDK of NXP MIMXRT595-EVK has a case based on MIPI DSI display. Through this case, one can understand how MIPI DSI hardware and software work together. This case connects the RK055AHD091 display screen to the MIMXRT595-EVK development board, performing some display-related applications.

The RK055AHD091 display screen uses the RM68200 driver, which differs from the previous article “Learning MIPI DSI from LCD Display Driver” in that RM68200 does not have FB (GRAM), so DSI can only be in Video Mode:

Below are the PINs of the RK055AHD091 display screen, where I2C is the access interface for the touch screen:

The screen is connected to the J44 interface on the back of the IMXRT595 development board:

The J44 interface matches the screen’s interface:

The basic architecture is as follows. It involves the LCDIF and DSI Host Controller (hereinafter referred to as HC) interfaces. The RM68200 on the display side is similar to what is introduced in “Learning MIPI DSI from LCD Display Driver“:

LCDIF integrates the Vivante DCNano IP, which is a display controller (DC). It connects to HC via the MIPI DBI/DPI interface, sending signals and display data to HC. HC converts it into DSI packets and transmits them to the display for display:

As can be seen, LCDIF has some basic functions of DC, such as hardware cursor, Dither/Gamma, etc. Its interface signals have some timing-related aspects. After these signals are given to HC, HC will reconstruct the timing DSI packet based on this information.

First, let’s look at the basic timing parameters:

#define DEMO_LCDIF_HSW 8#define DEMO_LCDIF_HFP 32#define DEMO_LCDIF_HBP 32#define DEMO_LCDIF_VSW 2#define DEMO_LCDIF_VFP 16#define DEMO_LCDIF_VBP 14

According to these values, they are configured into the following registers in LCDIF: Htotal, Vtotal, Vsync, Hsync, Panel Configuration:

Since DPI mode is used, it is necessary to select DPI in the Configuration register for DBI output.

And configure the DPI Pixel Format to the following registers:

These parameters determine the calculation of the pixel clock:

The pixel clock is (height + VSW + VFP + VBP) * (width + HSW + HFP + HBP) * frame rate.

The pixel clock setting of LCDIF comes from the SoC’s clock tree. Therefore, if a clock value is set, based on the above information, the refresh rate of LCDIF can be obtained. Below is the setting of the LCDIF clock:

static void BOARD_InitLcdifClock(void){    POWER_DisablePD(kPDRUNCFG_APD_DCNANO_SRAM);    POWER_DisablePD(kPDRUNCFG_PPD_DCNANO_SRAM);    POWER_ApplyPD();    /*     * The pixel clock is (height + VSW + VFP + VBP) * (width + HSW + HFP + HBP) * frame rate.     * Here use the aux0 pll (396MHz) as clock source, pixel clock set to 36MHz,     * then frame rate is:     *     * RK055IQH091: 60Hz     * RK055AHD091: 35Hz     */    CLOCK_AttachClk(kAUX0_PLL_to_DCPIXEL_CLK);    CLOCK_SetClkDiv(kCLOCK_DivDcPixelClk, 11);    mipiDsiDpiClkFreq_Hz = CLOCK_GetDcPixelClkFreq();    CLOCK_EnableClock(kCLOCK_DisplayCtrl);    RESET_ClearPeripheralReset(kDISP_CTRL_RST_SHIFT_RSTn);    CLOCK_EnableClock(kCLOCK_AxiSwitch);    RESET_ClearPeripheralReset(kAXI_SWITCH_RST_SHIFT_RSTn);}

Since the timing is the DPI information between LCDIF and HC, they also need to be set to the relevant registers in HC:

For RM68200, it is configured in the function RM68200_Init. The basic method is to write to HC’s APB interface, and HC will send DSI packets to initialize the RM68200. The configuration includes:

Setting LCM page0 initialization settings
Setting the number of lanes
Setting LCM initialization settings
Sending 29/00; 2c; 35/00

For example, setting the number of lanes:

/* Data lane number selection. */param[0] = 0x5FU;param[1] = 0x10U | (config-&gt;dsiLanes - 1U);status   = MIPI_DSI_GenericWrite(dsiDevice, param, 2);

MIPI_DSI_GenericWrite implements the sending of DSI Generic Write Packet to RM68200. The content inside Generic Write, as specified, is custom:

The 0x5F/0x10 specific meaning is not found in RM68200, it may be an undisclosed initialization sequence by the manufacturer.

The process of sending DSI packets is roughly as follows:

status_t DSI_TransferBlocking(MIPI_DSI_HOST_Type *base, dsi_transfer_t *xfer){    status = DSI_PrepareApbTransfer(base, xfer);    DSI_SendApbPacket(base);    /* Make sure the transfer is started. */    DSI_GetAndClearInterruptStatus(base, &amp;intFlags1Old, &amp;intFlags2Old);    /* Wait for transfer finished. by polling PKT_STATUS*/    DSI_GetAndClearInterruptStatus(base, &amp;intFlags1New, &amp;intFlags2New);    status = DSI_HandleResult(base, intFlags1Old | intFlags1New, intFlags2Old | intFlags2New, xfer);    return status;}

Simply put, it is operating HC’s registers:

TX_PAYLOAD
PKT_CONTROL
SEND_PACKET
PKT_STATUS
IRQ_STATUS

After sending, read the result operation registers:

PKT_RX_PKT_HEADER
PKT_RX_PAYLOAD

For example, TX_PAYLOAD:

SEND_PACKET:

After the initial setup, when LCDIF operates, it will read the display frame content from memory and send the pixel information to HC through the DPI interface at a fixed refresh rate, and the HC hardware will automatically convert it into DSI packets to send to the display, without software intervention.

Configure the memory address to LCDIF, completed by the following LCDIF-related registers:

As previously mentioned, the timing information needs to be set in both LCDIF and HC, so that LCDIF can send according to the rhythm, and HC can reconstruct the timing DSI packet sequence. It can be seen that LCDIF, as a hardware, bridges the memory pixel frame and HC through DPI, making continuous and stable display easier.

In addition, the HC’s Video Mode Burst Mode can be configured through the register CFG_DPI_VIDEO_MODE:

References:

RM69200 Data Sheet
SDK_2_14_0_EVK-MIMXRT595
IMXRT500 Reference Manual

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