MIPI (Mobile Industry Processor Interface) is the abbreviation for Mobile Industry Processor Interface. MIPI (Mobile Industry Processor Interface) is an open standard initiated by the MIPI Alliance for mobile application processors. The completed and planned specifications are as follows:
1. Terminology Explanation
• DCS (Display Command Set): DCS is a standardized command set used for command-mode display modules.
• DSI, CSI (Display Serial Interface, Camera Serial Interface)
• DSI defines a high-speed serial interface located between the processor and the display module.
• CSI defines a high-speed serial interface located between the processor and the camera module.
• D-PHY: Provides the physical layer definition for DSI and CSI.
2. DSI Layered Structure
DSI consists of four layers corresponding to D-PHY, DSI, DCS specifications. The layered structure diagram is as follows: • PHY defines the transmission medium, input/output circuits, clock, and signaling mechanisms. • Lane Management Layer: Sends and collects data streams to each lane. • Low-Level Protocol Layer: Defines how to frame, parse, and error detection, etc. • Application Layer: Describes high-level encoding and parsing of data streams.
3. Command and Video Modes • DSI compatible peripherals support Command or Video operating modes, which mode is determined by the architecture of the peripheral. • Command mode refers to sending commands and data to a controller with display memory. The host indirectly controls the peripheral through commands. The command mode uses a bidirectional interface. • Video mode refers to transmitting real-time pixel streams from the host to the peripheral. This mode can only be transmitted at high speed. To reduce complexity and save costs, systems that only use video mode may only have a unidirectional data path.
1. D-PHY describes a synchronous, high-speed, low-power, low-cost PHY.
• A PHY configuration includes
• A clock lane
• One or more data lanes
• The PHY configuration of the two lanes is shown in the following figure.
• The three main types of lanes are
• Unidirectional clock lane
• Unidirectional data lane
• Bidirectional data lane
• D-PHY Transmission Modes
• Low-Power signal mode (for control): 10MHz (max)
• High-Speed signal mode (for high-speed data transmission): 80Mbps ~ 1Gbps/Lane
• The minimum data unit defined by the D-PHY low-level protocol is one byte.
• When sending data, the low bit must come first, followed by the high bit.
• D-PHY is suitable for mobile applications.
• DSI: Display Serial Interface
• One clock lane, one or more data lanes
• CSI: Camera Serial Interface
2. Lane Module
• PHY consists of D-PHY (Lane module)
• D-PHY may include:
• Low-Power Transmitter (LP-TX)
• Low-Power Receiver (LP-RX)
• High-Speed Transmitter (HS-TX)
• High-Speed Receiver (HS-RX)
• Low-Power Collision Detector (LP-CD)
• The three main lane types are
• Unidirectional clock lane
• Master: HS-TX, LP-TX
• Slave: HS-RX, LP-RX
• Unidirectional data lane
• Master: HS-TX, LP-TX
• Slave: HS-RX, LP-RX
• Bidirectional data lane
• Master, Slave: HS-TX, LP-TX, HS-RX, LP-RX, LP-CD
3. Lane States and Voltages
• Lane states
• LP-00, LP-01, LP-10, LP-11 (single-ended)
• HS-0, HS-1 (differential)
• Lane voltages (typical)
• LP: 0-1.2V
• HS: 100-300mV (200mV)
4. Operating Modes
• Three operating modes for data lanes
• Escape mode, High-Speed (Burst) mode, Control mode
• Possible events starting from the stopped state of the control mode are:
• Escape mode request (LP-11→LP-10→LP-00→LP-01→LP-00)
• High-Speed mode request (LP-11→LP-01→LP-00)
• Turnaround request (LP-11→LP-10→LP-00→LP-10→LP-00)
•Escape mode is a special operation of the data lane in LP state
• In this mode, additional functions can be entered: LPDT, ULPS, Trigger
• The data lane enters Escape mode through LP-11→LP-10→LP-00→LP-01→LP-00
• Once in Escape mode, the sender must send a single 8-bit command to respond to the requested action
• Escape mode uses Spaced-One-Hot Encoding
• Ultra-Low Power State • In this state, lines are in an idle state (LP-00) • The clock lane’s ultra-low power state • The clock lane enters ULPS state through LP-11→LP-10→LP-00 • Exits this state through LP-10 → TWAKEUP →LP-11, with a minimum TWAKEUP time of 1ms
• High-speed data transmission • The behavior of sending high-speed serial data is called high-speed data transmission or triggering (burst)
• All lanes gate synchronization start, the end time may be different. • The clock should be in high-speed mode
• Transmission process under various operating modes
• The process of entering Escape mode: LP-11→LP-10→LP-00→LP-01→LP-00→Entry Code → LPD (10MHz) • The process of exiting Escape mode: LP-10→LP-11 • The process of entering high-speed mode: LP-11→LP-01→LP-00→SoT(00011101) → HSD (80Mbps ~ 1Gbps) • The process of exiting high-speed mode: EoT→LP-11 • Control mode – BTA transmission process: LP-11→LP-10→LP-00→LP-10→LP-00 • Control mode – BTA reception process: LP-00→LP-10→LP-11
• State transition relationship diagram
1. DSI is a lane scalable interface, with 1 clock lane/1-4 data lanes • DSI compatible peripherals support 1 or 2 basic operating modes: • Command Mode (similar to MPU interface) • Video Mode (similar to RGB interface) – Data must be transmitted using high-speed mode, supporting three formats of data transmission
• Non-Burst synchronous pulse mode • Non-Burst synchronous event mode • Burst mode
• Transmission modes: • High-speed signaling mode • Low-power signaling mode – only uses data lane 0 (the clock is derived from DP, DN XOR). • Frame types • Short frame: 4 bytes (fixed) • Long frame: 6~65541 bytes (variable)
• Two data lanes high-speed transmission example
2. Short frame structure • Frame header (4 bytes) • Data Identifier (DI) 1 byte • Frame data – 2 bytes (fixed length of 2 bytes) • Error Detection (ECC) 1 byte • Frame size • Fixed length of 4 bytes
3. Long frame structure • Frame header (4 bytes) • Data Identifier (DI) 1 byte • Data count – 2 bytes (number of data fills) • Error Detection (ECC) 1 byte • Data fill (0~65535 bytes) • Length = WC * bytes • Frame tail: checksum (2 bytes) • Frame size: • 4 + (0~65535) + 2 = 6 ~ 65541 bytes
1. MIPI DSI signal measurement diagram in Low Power mode
2. MIPI’s D-PHY and DSI transmission methods and operating modes
• D-PHY and DSI transmission modes
• Low-Power signal mode (for control): 10MHz (max)
• High-Speed signal mode (for high-speed data transmission): 80Mbps ~ 1Gbps/Lane
• D-PHY operating modes
• Escape mode, High-Speed (Burst) mode, Control mode
• DSI operating modes
• Command Mode (similar to MPU interface) • Video Mode (similar to RGB interface) – Data must be transmitted using high-speed mode
3. Summary
• Transmission modes and operating modes are different concepts
• Video Mode operating mode must use High-Speed transmission mode
• Command Mode operating mode does not specify the use of High-Speed or Low Power transmission modes, or
• Even if the external LCD module is in Video Mode, it is usually still initialized in Command Mode to read and write registers, as data is less prone to error and easier to measure at low speeds.
• Video Mode can also use High-Speed to send commands, and Command Mode operating mode can also use High-Speed, but it is not necessary to do so.
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