A Comprehensive Guide to LCD Screen and MIPI-DSI Parameter Calculation

Introduction

As an important part of the functionality of the i.MX series chips, we will be detailing the workings of display-related modules based on the i.MX8MP over the coming period, including the steps to enable customized screens and potential issues that may arise. This article will focus on MIPI-DSI, further calculating the parameters required for enabling MIPI-DSI interface screens.

LCD Related Parameter Calculation

1.1 Calculating Pixel Clk and VIDEO PLL

In a previous article, Hand-on Series Display Part (1) – Analysis of LCD and OLED Display Parameters, we analyzed the working principles of LCD screens and the meanings of various parameters. In this article, we will first calculate the total height and total width of a frame based on the screen parameters:

Total_Height =

VSYNC + VBP + Active_Height + VFP

Total_Width =

HSYNC + HBP + Active_Width + HFP

Subsequently, we can obtain the amount of data (Frame_Bit, in bits) needed for one frame based on the total length, total width, and the depth of display pixels (Pixel_Depth, unit bpp, bits per pixel):

Frame_Bit =

Total_Width x Total_Height x Pixel_Depth

For colored images, the pixel depth determines the number of possible colors for each pixel. Typically, each pixel of a colored image is represented by three components: R, G, and B. If each component uses 8 bits (RGB888), then a pixel is represented by 24 bits, and its pixel depth is 24 bpp (bits per pixel). In this case, the pixel can represent one of 2 to the power of 24 colors. Therefore, we can conclude that the greater the pixel depth of a pixel, the more colors it can represent. Below are some common color formats we often encounter:

RGB888 – Pixel Depth = 24 bpp
RGB666 – Pixel Depth = 18 bpp
RGB565 – Pixel Depth = 16 bpp

Additionally, a video stream consists of a series of display frames with fixed timing intervals. Therefore, we can calculate the number of pixels per second by introducing the frame rate (fps) to obtain the pixel clock (Pixel_Clk):

Pixel_Clk =

Total_Width x Total_Height x fps

Furthermore, we can calculate the total system bandwidth, which is the amount of data that needs to be transmitted in one second (in bps):

Bit_per_Second = Pixel_Clk x Pixel_Depth

We typically set the Pixel_Clk obtained from dividing the VIDEO PLL, and VIDEO PLL is derived from the CCM. Therefore, we need to further calculate the relationship between the VIDEO PLL required for the screen and its clock source and configure it:

Fvco = (m + k / 65536) x Fin / (p x (2^s))

Notice:

N.1 Different SOCs use different frequency drivers. Here, for the i.MX8MP, if you need to add the expected generated PLL values, you can add them in the path drivers/clk/imx/clk-pll14xx.c.

N.2 Here, Fvco refers to the VIDEO PLL, and the Fin corresponding to the VIDEO PLL is usually a 24M crystal oscillator. We will subsequently provide a detailed analysis based on the settings of RM67191 on the i.MX8MP.

Note & Porting Suggestion：Based on the method of generating Pixel_Clk by VIDEO PLL, we usually set the value of VIDEO PLL to be an integer multiple of Pixel_Clk. For detailed reasons, please refer to the ‘Target Register (CCM_TARGET_ROOTn)’ register in the manual. We will subsequently provide a detailed analysis based on the settings of RM67191 on the i.MX8MP.

When calculating the Clk-related parameters, we not only consider the effective resolution but also the front porch, back porch, and sync signals. However, it is important to note that when we calculate the size of the frame buffer needed to store one frame of image, we only need to consider the actual effective resolution and pixel depth:

Buffer_Size =

Active_Height x Active_Width

x Bits_per_Pixel

Based on RM67191 MIPI DSI Parameter Calculation

2.1 Calculation and Setting of Pixel Clk

When adapting to a new screen, we can usually obtain screen-related information (datasheet, schematics, timing, and driver reference code) from the screen manufacturer. Below, we take the i.MX8MP EVK and the accompanying RM67191 DSI screen as an example:

RM67191 Driver:

drivers/gpu/drm/panel/panel-raydium-rm67191.c
DTB:

arch/arm64/boot/dts/freescale/imx8mp-evk-rm67191.dts

By analyzing the relevant data provided by the screen manufacturer, we can usually obtain the following data and perform further calculations:

HFP, H-SYNC, HBP and HACTIVE
VFP, V-SYNC, VBP and Active Height
Pixel_Depth = 24 bpp
fps = 60
lane_number =4

First, we can calculate the total number of pixels in both length and width of one frame displayed on the screen

Total_Width =

1080+2+20+34 = 1136 Pixels

Total_Height = 1920+10+2+4 = 1936 Pixels

According to the previous formula, the pixel clock required for a frame rate of 60 FPS can be obtained by multiplying the total pixels per frame by the required frame rate:

Pixel_Clk =

1136 * 1936 x 60 = 131,957,760 Hz

Pixel_Clk ≈ 132MHz

The pixel format of the screen is RGB888, so the pixel depth is 24. We can also obtain the bandwidth:

Bit_per_Second =

131,957,760 x 24 = 3,166,986,240 bps

First, for RM67191, we set Pixel_Clk and OLED screen related parameters through the RM67191 driver (drivers/gpu/drm/panel/panel-raydium-rm67191.c):

static const struct drm_display_mode default_mode = {        .clock = 132000,        .hdisplay = 1080,        .hsync_start = 1080 + 20,        .hsync_end = 1080 + 20 + 2,        .htotal = 1080 + 20 + 2 + 34,        .vdisplay = 1920,        .vsync_start = 1920 + 10,        .vsync_end = 1920 + 10 + 2,        .vtotal = 1920 + 10 + 2 + 4,        .width_mm = 68,        .height_mm = 121,        .flags = DRM_MODE_FLAG_NHSYNC |                 DRM_MODE_FLAG_NVSYNC,};

Where clock is the Pixel Clk we calculated earlier, which is 132MHz. The subsequent screen parameters are those introduced in the previous article, Hand-on Series Display Part (1) – Analysis of LCD and OLED Display Parameters.

2.2 VIDEO_PLL Setting

/* VIDEO_PLL m p s k*/static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {        PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),        PLL_1443X_RATE(650000000U, 325, 3, 2, 0),        PLL_1443X_RATE(594000000U, 198, 2, 2, 0),        PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),        PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),        PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),};

After setting Pixel_Clk, we need to further set the VIDEO_PLL. If the VIDEO_PLL value we expect to use is not in the above PLL driver, we also need to add the VIDEO_PLL and its multiplier values m, k, p, and s in the structure. Below is a calculation demonstration using the VIDEO PLL value of ‘1039500000’:

Fvco = (m + k / 65536) x Fin / (p x (2^s))

1039.5MHz = (m + k / 65536) x 24MHz

/ (p x (2^s))

m = 173, k = 16384, p = 2 & s = 1

In addition to adding the VIDEO PLL we are using in the structure, we also need to set it in the DTB:

media_blk_ctrl: blk-ctrl@32ec0000 {        &lt;...&gt;        assigned-clocks = &lt;&amp;clk IMX8MP_CLK_MEDIA_AXI&gt;,                          &lt;&amp;clk IMX8MP_CLK_MEDIA_APB&gt;,                          &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP1_PIX&gt;,                          &lt;&amp;clk IMX8MP_CLK_MEDIA_DISP2_PIX&gt;,                          &lt;&amp;clk IMX8MP_VIDEO_PLL1&gt;;        assigned-clock-parents = &lt;&amp;clk IMX8MP_SYS_PLL2_1000M&gt;,                                 &lt;&amp;clk IMX8MP_SYS_PLL1_800M&gt;,                                 &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;,                                 &lt;&amp;clk IMX8MP_VIDEO_PLL1_OUT&gt;;        assigned-clock-rates = &lt;500000000&gt;, &lt;200000000&gt;,                               &lt;0&gt;, &lt;0&gt;, &lt;1039500000&gt;;  };

Notice: This article is based on LF6.6.3 for settings and explanations, and the settings methods may vary between different versions. For specific settings, please refer to the actual BSP version used.

2.3 Pixel Clk and VIDEO_PLL

Previously, we mentioned that the values of Pixel_Clk and VIDEO_PLL usually need to be in integer multiples of each other. Here, we will explain this in detail at the register level. First, by analyzing the i.MX8MP CLK driver (linux-imx/drivers/clk/imx/clk-imx8mp.c), we can see that the offset of ‘media_disp1_pix’ is 0xbe00, as shown in the manual below:

In the above figure, we can see that there are several different options for the clock source of Pixel_Clk. Typically, we choose to generate Pixel_Clk from VIDEO_PLL. Of course, we can also choose a crystal oscillator or other PLL. The following figure shows the frequency division method of CCM, which obtains the output clock by dividing the input clock by an integer from 1 to 64. This is why during the display adaptation process, we typically set VIDEO_PLL to be an integer multiple of Pixel_Clk.

A Comprehensive Guide to LCD Screen and MIPI-DSI Parameter Calculation

In addition to understanding the frequency division relationship between VIDEO_PLL and Pixel_Clk at the register level, we can also confirm whether our settings are successful by reading the register values.

# /unit_tests/memtool -32 0x3038be00 10x3038BE00:  11000007

By comparing the above-read register value, ’11000007′, with the description in the manual, we can determine:

ENABLE(28) bit is 1: enables the clock root
MUX(26-24) bits are 001: Source is set to VIDEO_PLL_CLK
POST_PODF(5-0) bits are111: Pixel_Clk is obtained by dividing VIDEO_PLL by 8

2.4 Verifying Pixel Clk and VIDEO_PLL Settings through Clock Tree

In addition to accessing the register values, we can also see the set VIDEO PLL and Pixel_clock to confirm whether they are set successfully by the command cat /sys/kernel/debug/clk/clk_summary.

 osc_24m                                         15       15       0    24000000          0     0  50000         Y    video_pll1_ref_sel                           1        1        0    24000000          0     0  50000         Y       video_pll1                                1        1        0  1039500000          0     0  50000         Y          video_pll1_bypass                      1        1        0  1039500000          0     0  50000         Y             video_pll1_out                      1        1        0  1039500000          0     0  50000         Y                media_disp1_pix                  1        1        0   129937500          0     0  50000         Y                   media_disp1_pix_root_clk      1        1        0   129937500          0     0  50000         Y

Notice: Here, it can be seen that due to the default BSP, the setting of Video_PLL and Pixel_Clk is not in integer multiples, and it will be automatically adjusted to a new approximate value. To avoid the new approximate value deviating too much from the set value, the drivers for DSI and LCDIF will verify whether the approximate value is within a certain percentage range (for detailed information, please refer to the corresponding driver).

Conclusion

This article analyzed DSI, and using RM67191 as an example, calculated the parameters needed to enable MIPI-DSI screens. For any questions or suggestions regarding the article, please contact the author at [email protected]. We welcome discussions via email. In the coming period, we will gradually update the parameter analysis and calculations related to display modules (LVDS and MIPI-DSI), so stay tuned to the official account for the latest updates. If you have any questions about displays or other modules, please feel free to reach out for discussion.

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