Research and Implementation of MIPI-DSI in AMOLED Display Driver IC
ZHANG Jie, YANG Guozhong
Abstract: MIPI-DSI (MIPI-Display Serial Interface) is a solution provided by the MIPI Alliance specifically for displaying mobile devices. MIPI-DSI can be divided into four layers, from data transmission to data application, namely PHY Layer, Lane Management Layer, Low Level Protocol Layer, and Application Layer. This article analyzes the implementation of MIPI-DSI in AMOLED display driver IC using a layered design concept and discusses the design challenges involved.
Keywords: integrated circuit design, display driver, data reading.
Index Terms: integrated circuit design, display driver, data reading.
1 AMOLED
1.1 AMOLED Technology
AMOLED (Active-matrix organic light-emitting diode) is a display technology. OLED (organic light-emitting diode) describes a specific type of thin-film display technology that uses organic electroluminescent materials; AM (active-matrix) refers to the pixel addressing technology behind it.
AMOLED technology has gradually been adopted in high-end smartphones and other small consumer electronics due to its wide color gamut, high contrast, ultra-thin form factor, low power consumption, and flexibility. Moreover, AMOLED technology continues to develop towards low power consumption, low cost, and larger sizes.
1.2 Display Interface Selection for AMOLED Displays
The MIPI (Mobile Industry Processor Interface) is an open standard and specification initiated by the MIPI Alliance for mobile application processors. The MIPI Display Serial Interface (MIPI-DSI) is a solution specifically provided by the MIPI Alliance for the display of mobile devices.
The earliest MIPI-DSI supported a data path bandwidth of up to 1 Gbps, capable of supporting displays with a maximum resolution of 2k. As the size, resolution, and refresh rate of AMOLED displays continue to increase, the MIPI Alliance has updated the DSI protocol, allowing for a maximum data path bandwidth of 1.5 Gbps without adding extra logic. The new DSI protocol also proposes two methods to support higher resolution displays: (1) increasing the bandwidth of the data path; (2) proposing a multi-port solution to increase the support for high resolution without increasing the bandwidth.
Additionally, e-DP (embedded DisplayPort), primarily used in laptops and other embedded devices, is gradually being applied to larger AMOLED displays.
This article mainly discusses and studies the current most widely used solution for small display interfaces, MIPI-DSI.
2 Overview of MIPI-DSI
MIPI-DSI can be divided into four layers, from data transmission to data application, namely PHY Layer, Lane Management Layer, Low Level Protocol Layer, and Application Layer.
2.1 PHY Layer
MIPI-DSI has one clock lane and four data lanes. The clock lane provides the clock for data transmission in High Speed mode. The data lanes transmit data in a serial manner, with the Transmitter (Tx) and Receiver (Rx) synchronizing data transmission through special data streams such as SoT (Start of Transmission) and EoT (End of Transmission). Data transmission can occur in Low Power mode and High Speed mode. In Low Power mode, the bandwidth is less than 20 Mbps, primarily used for sending data with low bandwidth requirements, which reduces power consumption. High Speed mode has a bandwidth of up to 1.5 Gbps without adding extra logic. Additionally, Lane 0 supports bidirectional transmission, allowing Tx to obtain necessary information from Rx and Rx to provide feedback on the current status to Tx.
2.2 Lane Management Layer
The Tx side uses a distributor to split the video or command data to be transmitted into 1/2/3/4 lanes, while the Rx side uses a merger to combine the received data back into the original data for video and command decoding.
MIPI-DSI allows for the selection of 1, 2, 3, or 4 data lanes based on the bandwidth requirements of different applications. If the bandwidth requirement is low, fewer lanes can be chosen to transmit data, saving power; if the bandwidth requirement is high, all four lanes must work together. Table 1 calculates the theoretical bandwidth required for video at 2k resolution (1080×2160＠60 Hz) for RGB-24 bpp, RGB-18 bpp, and RGB-16 bpp under four data lane modes, allowing users to determine which data lane mode to select based on MIPI-DSI’s maximum data lane bandwidth of 1.5Gbps.
3 MIPI-DSI_Rx Layered Design
The DSI interface in the AMOLED display driver IC is the Rx side of MIPI-DSI, responsible for receiving video data and commands sent from the Tx side and delivering them to the subsequent pixel processing module and instruction execution module within the chip.
4 Conclusion
This article only discusses the MIPI interface in AMOLED display driver ICs. The AMOLED driver IC includes both digital and analog circuit components. The digital circuit part includes not only MIPI-DSI but also pixel processing algorithms; in chips supporting command mode, it includes compression and decompression of pixel data. The compression of pixel storage can reduce the number of storage units within the chip, thereby lowering manufacturing costs. The analog part includes power management and driving of AMOLED light-emitting diodes, etc. A more in-depth discussion and research are needed for the complete realization of the driver chip. Currently, the chip has successfully passed typeout, using UMC 40 nm technology and has entered the laboratory testing phase.
References
[1] MIPI Alliance Specification for Display Serial Interface (DSI), version 1.3[M]. MIPI Alliance, Inc.
[2] MIPI Alliance Specification for Display Command Set (DCS), version 1.3[M]. MIPI Alliance, Inc.
[3] MIPI Alliance Specification for D-PHY, version 1.2[M]. MIPI Alliance, Inc.
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