Introduction

In the MIPI communication protocol, several lanes transmit data simultaneously within a unit time. According to the DSI specification, there can be at least one and at most four data channels. Therefore, we can expand the previously calculated parameters to obtain the number of bits transmitted per second for one lane in MIPI-DSI, known as Data Rate Per Lane (DRPL):

Bit_Clk must be greater than or equal to the calculated value of DRPL, which is typically generated by the D-PHY PLL. Subsequently, D-PHY uses Bit_Clk to generate MIPI_Clock.

As mentioned earlier, the MIPI-DSI interface samples DDR (sampling on both the rising and falling edges), so the MIPI transmission clock is half of the data rate per channel. The MIPI transmission clock (MIPI_Clock) can also be summarized as:

MIPI_Clock = DRPL/2

The output frequency of the D-PHY CLOCK is half of DRPL, meaning the transmission clock frequency (CLK_P and CLK_N) for MIPI screens is the value from the above formula. This value is also what we typically measure at the MIPI-DSI end CLK_N or CLK_P.

We usually also need to set the D-PHY Phase Locked Loop (PLL) Clock to generate the Bit Clock through frequency multiplication. When calculating the PLL Clock, the input is F_in, which is an external input clock given to the D-PHY PLL, usually provided by the CCM divider. The output clock F_out is the previously calculated Bit Clock:

Thus, we can obtain the parameter information needed for frequency multiplication through the above formulas. In the i.MX8MP, this part of the parameters is automatically calculated through the drivers/gpu/drm/bridge/sec-dsim.c driver in the sec_mipi_dsim_calc_pmsk function. Additionally, it is important to note that the parameters in the formula must meet the ranges listed in the following table:

Notice: The F_in mentioned here is derived from the CCM divider, and detailed information can be found in the relevant Clk Root’s ‘Target Register (CCM_TARGET_ROOTn)’ register. In the following sections, we will detail the RM67191.

• Pixel_Clk = 131,957,760 Hz ≈ 132MHz

• Bit_per_Second = 3,166,986,240 bps

We use 4 lanes for data transmission, so we can obtain the number of bits transmitted per second for one lane, i.e., the Data Rate Per Lane (DRPL):

DRPL = 3,166,986,240/4 = 791,746,560 Hz

Bit_Clk >= 791,746,560 Hz ≈ 792 MHz

We can further calculate the output clock of DSI-PHY as:

MIPI_Clock =

791,746,560/2=395,873,280 Hz

MIPI_Clock ≈ 396 MHz

792,000,000 = 12,000,000 x (M/(P x 2^S))

# /unit_tests/memtool -32 0x32e60094 10x32e60094: 00804842 

• PllEn(23) bit is 1: Enable PLL

• PMS(19-1) bits are 0000 0100 1000 0100 001:

• P (19-14) bits are 0000 01: The value of P is ‘1’, consistent with the previously set value in the driver.

• M (13-4) bits are 00 1000 0100: The value of M is ‘132’, consistent with the previously set value in the driver.

• S (3-1) bits are 001: The value of S is ‘1’, consistent with the previously set value in the driver.

mipi_dsi: mipi_dsi@32e60000 {                  ...  clocks = <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK>,        <&media_blk_ctrl IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF>;        clock-names = "cfg", "pll-ref";        assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;        # PHY_REF_CLK 的源        assigned-clock-parents = <&clk IMX8MP_CLK_24M>;        # PHY_REF_CLK 的值        assigned-clock-rates = <12000000>;  ...};

# /unit_tests/memtool -32 0x3038bd80 10x3038BD80:  10000001

• ENABLE(28) bit is 1：Enableclock root

• MUX(26-24) bits are 000: Source is set to 24M_REF_CLK

• POST_PODF(5-0) bits are 00001: media_mipi_phy1_ref is obtained by dividing 24M_REF_CLK by two, which gives us the previously set value of12MHz.

 osc_24m                             11       11        0    24000000          0     0  50000         Y    media_mipi_phy1_ref                       1        1        0    12000000          0     0  50000         Y

Notes: The Clock Tree can only see the D-PHY input clock, and cannot view the subsequent D-PHY output Bit_Clk and MIPI_Clock. This is because the subsequent operations are not derived from the CCM divider, but are obtained from the frequency multiplication of the D-PHY related driver.

Notice：In the MIPI-DSI driver, PHY_REF_CLK is fixed at 12MHz. It cannot be modified by changing the value of CLK in the DTB separately:

/* fixed phy ref clk rate */#define PHY_REF_CLK             12000

Conclusion