RM68120 is a single-chip TFT LCD display driver produced by Raydium Semiconductor. With over 1M of GRAM memory, it can support a display resolution of 480×864. The input interfaces include DPI, DBI, and DSI. Therefore, starting with MIPI DSI provides a different perspective on the problem, leading to different understandings:

The DBI interface generally has the display module (i.e., RM68120 here) equipped with a DC (Display Controller) and FB (Frame Buffer). There are three types of interfaces: Type A – parallel Moto 6800 bus; Type B – parallel Intel 8080 bus; Type C – serial SPI interface.

Thus, the DBI interface of RM68120 allows the upstream display host to load display content onto RM68120, which is responsible for refreshing the display on the screen. Some command words can also be sent through this parallel interface. These command words are defined by DCS.

The DPI interface generally does not have DC and FB in the display module, with the host directly sending RGB display pixels from the parallel interface to the display module (i.e., RM68120 here). Since the display content is transmitted frame by frame, with each frame composed of several lines, and the parallel interface can transmit a maximum of 24 bits at a time, it takes several clock cycles to complete the transmission of one frame. Each clock cycle is a pixel clock, and during the transmission process, timing control signals such as Vsync and Hsync are used to identify which pixel the 24-bit content corresponds to within the frame. The host needs to continuously transmit frame content to maintain a certain refresh rate, ensuring stability of the displayed content. The 24-bit information on the parallel interface is interpreted as RGB565 or RGB888, etc., defined by the pixel format.

The DSI interface integrates DBI+DCS and DPI, mainly merging the concepts, where DBI+DCS is used in Command mode, while DPI is in Video mode. The transmission interface is based on differential, lane-based serial transmission. More details will be elaborated later. Since the transmission is serial, if an operation requires a response from the display module, it incurs more delay compared to the purely DBI method, such as reading the frame buffer from the display module, but such application scenarios are not common.

The interface selection of RM68120 is determined by the pin IM[3:0], as shown below:

The command and data of the parallel Intel 8080 DBI (Type B DBI) are transmitted on the data bus DB[23:0]. CSX is valid when low. The WRX line controls the write timing, while RDX controls the read timing. DCX indicates whether the transmission is a command or data:

When reading data, we see that Host to LCD first sends CMD on D[23:0], and then LCD to Host returns data on DB[23:0]. Note that the switch of DCS indicates the switch between command and data transmission on DB:

The following diagram shows how Vsync, Hsync, DE, and PCLK (DotClk) cooperate to transmit pixels on DB:

https://www.cnblogs.com/vedic/p/10679464.html

Earlier, it was mentioned that DSI integrates DBI, DPI, and DSI, but it is only a conceptual reference, not an interface reuse. The original text in the spec states: DSI specifies the interface between a host processor and a peripheral such as a display module. It builds on existing MIPI Alliance specifications by adopting pixel formats and command set specified in DPI-2, DBI-2 and DCS standards.

DSI will mention Video Mode and Command Mode, and their corresponding relationships are:

• DSI Command Mode: Transmits commands and data/pixels on the lane in accordance with DBI. The commands here are defined by DCS.

• DSI Video Mode: Transmits RGB pixel data on the lane in accordance with DPI, in conjunction with additional signals for timing control.

It should be noted that DBI/DPI transmits information on the parallel interface, whereas DSI transmits on the serial lane. For Video Mode, the timing is not provided by additional signals like Hsync, Vsync, DE, PCLK, etc., but is achieved by sending timing control packets on the lane: With this format, the goal is to accurately convey DPI-type timing over the DSI serial Link. This includes matching DPI pixel-transmission rates, and widths of timing events like sync pulses. Accordingly, synchronization periods are defined using packets transmitting both start and end of sync pulses.

Below is the timing for Non-Burst Mode with Sync Pulses:

It can be seen that there are many timing packets before and after transmitting RGB pixel data.

It appears that Video Mode and Command Mode do not have any essential differences; both send packets on the lane. Thus, some DSI Host Controllers may also include a small amount of command control in Video Mode: Some display modules that use Video Mode in normal operation also make use of a simplified form of Command Mode, when in low-power state. These display modules can shut down the streaming video interface and continue to refresh the screen from a small local frame buffer, at reduced resolution and pixel depth. The local frame buffer shall be loaded, prior to interface shutdown, with image content to be displayed when in low-power operation. These display modules can switch mode in response to power-control commands.

Finally, let’s compare the timing differences of the three methods in Video Mode

It can be seen that in Burst Mode, RGB is transmitted in concentrated form, allowing for more opportunities to enter low-power states. Since Video Mode relies on the host side for refreshing, it does not save bandwidth.

In contrast, Command Mode, as the display module maintains the content refresh, can save bandwidth.