MIPI CSI-2 (MIPI Camera Serial Interface 2) is the most widely used camera interface in the mobile and other markets. It is widely adopted for its ease of use and support for a wide range of high-performance applications, including 1080p, 4K, 8K, and higher video and high-resolution photography. It consists of protocol layer, application layer, and physical layer. The physical layer primarily uses D-phy and C-phy.
MIPI DSI (MIPI Display Serial Interface) defines a high-speed serial interface between the host processor and the display module. This interface allows manufacturers to integrate displays for high performance, low power consumption, and low electromagnetic interference (EMI), while reducing pin count and maintaining compatibility among different vendors. Designers can use MIPI DSI to provide excellent color rendering for the most demanding image and video scenarios, and it also employs D-phy for its physical layer.
D-phy is the physical layer standard published by the MIPI Alliance’s physical layer group, which also publishes other physical layer standards such as A-phy, C-phy, and M-phy.
The D-phy V1.0 standard states that it uses two modes for data transmission: high-speed mode (High Speed, HS) and low-power mode (Low Power, LP), with different transmission levels and mechanisms for each mode. Each data channel in D-phy uses two lines (the HS and LP share the same transmission lines), and the clock channel also uses two lines. This indicates that a minimum configuration requires four lines. In high-speed mode, each channel is terminated on both sides and driven by low-swing differential signals (SLVS). In low-power mode, all wires operate in a single-ended and non-terminated manner.
In HS mode, the rate can reach 500Mbps in DDR (dual-edged data transmission) mode. By adopting burst mode communication, the effective data throughput can be reduced. The maximum data rate in low-power mode is 10Mbps.
The D-PHY electrical sublayer indicates that high-speed signals (HS) use a low-swing differential level transmission of about 200 mV, while low-power signals (LP) use a larger single-ended level transmission of about 1.2V.
The circuit structure of the HS transmitter is shown in the diagram, consisting of two CMOS differential output circuits. From its DC parameters, the differential voltage swing is 140~270mV, with a typical value of 200mV, and the single-ended output impedance is 40~62.5 ohm. This parameter helps us design the receiving end circuit board with proper impedance control and matching to ensure signal integrity. The Lattice FPGA does not have such IO buffer internally, so it can only use other IO buffer for level conversion to meet these requirements.
The LP transmitter circuit diagram uses the LVCOMS12 structure output. The Lattice FPGA has LVCOMS12 IO buffer, which, along with external termination resistors, can meet the output impedance requirement of 110 Ohm.
The receivers of HS and LP are not much different from ordinary LVDS and CMOS receivers. Since Lattice can receive 200mV SLVS, it is sufficient to select a fixed IO bank. It is worth mentioning that Lattice devices have limited trueLVDS pins, and using LVDS25E requires external termination resistors, with the termination resistor Zid generally being 100 ohm, consistent with the external termination of LVDS. Of course, the rates that LVDS and LVDS25E can receive are different, and this needs to be noted.
The Lattice MIPI csi-2 and DSI require additional designs and solutions for other devices apart from using crosslink devices, as other devices need to add and design the D-phy electrical sublayer themselves, because crosslink devices are more like a programmable ASIC, while ordinary FPGA do not have such physical resources as shown in the diagram.
The design of the MIPI D-phy transmitter needs to use the resources of LVDS25E, which is constructed through the Lattice 8mA CMOS output buffer in a bridge circuit. By using an external resistor to create a shunt network, the output of LVDS can be simulated.
By changing this resistor network, the output level of D-phy HS can be simulated along with LP levels, with the LP level using the IO buffer as LVCMOS12. Official data from Lattice suggests RH=330 ohm and RL=50 ohm, and the power supply for this bank should be 2.5V. If 3.3V is used, the design must be adjusted according to the rate and signal integrity.
For the receiver, since Lattice‘s LVDS IO buffer supports SLVS levels, it is sufficient to use LVCMOS12 IO buffer for the LP receiver, along with an external termination resistor of RT=50 ohm. When LVDS IO resources are insufficient, LVDS25E can be used, which will require external 100 ohm resistors, and after integrating the MIPI CSI-2 and MIPI DSI projects, layout and routing errors may occur, which will need to be optimized in the internal layout and routing of the FPGA.
