AMD Announces Zen 6 EPYC ‘Venice’ as the First HPC Chip to Tape Out and Enter Production on TSMC’s N2 Process

This article is reprinted from: IT HomeAuthor: Su Bo

On the 14th local time, AMD announced that its next-generation (Zen 6) EPYC processor, codenamed ‘Venice’, has become the first HPC (High-Performance Computing) chip to tape out and enter production on TSMC’s 2nm N2 process node. The EPYC ‘Venice’ processor is expected to be launched next year.

AMD also stated that its fifth-generation EPYC (EPYC) processors have successfully entered production and been validated at TSMC’s Arizona Fab 21 wafer fab. From the perspective of Fab 21’s process level, this should refer to the 4nm ‘Zen 5’ standard core version.

AMD Announces Zen 6 EPYC 'Venice' as the First HPC Chip to Tape Out and Enter Production on TSMC's N2 Process

AMD Chair and CEO Dr. Lisa Su stated:

TSMC has been an important partner for us over the years, and our deep collaboration with TSMC’s R&D and manufacturing teams has enabled AMD to continuously deliver leading products that push the limits of HPC.

Becoming a leading HPC customer for TSMC’s N2 process and TSMC Arizona Fab 21 is an excellent example of our close collaboration, driving innovation, and providing advanced technologies that power the future of computing.

TSMC Chairman and CEO Dr. C. C. Wei stated:

We are honored that AMD has become a major HPC customer for our advanced 2nm (N2) process technology and TSMC Arizona wafer fab.

Through collaboration, we are driving significant technological upgrades that enhance the performance, energy efficiency, and yield of high-performance chips. We look forward to continuing our close partnership with AMD to usher in the next era of computing.

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